Implementation of a Modular Neural Network in a Multiple Processor System on Chip to Classify Electric Disturbance

Danniel Cavalcante Lopes, Rafael Marrocos Magalhães, Jorge Dantas de Melo, Adrião Duarte Dória Neto

2009

Abstract

This paper shows the effectiveness of a modular neural network composed of multilayers experts trained with a hybrid algorithm implemented in a multiprocessor system on chip. The network is applied on the classification of electric disturbances. The objective is to show that, even a FPGA with hardware restrictions, it could be used to implement a complex problem, when parallel processing is used. To improve the system performance was used four soft processors with a shared memory.

References

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Paper Citation


in Harvard Style

Cavalcante Lopes D., Marrocos Magalhães R., Dantas de Melo J. and Dória Neto A. (2009). Implementation of a Modular Neural Network in a Multiple Processor System on Chip to Classify Electric Disturbance . In Proceedings of the 5th International Workshop on Artificial Neural Networks and Intelligent Information Processing - Volume 1: Workshop ANNIIP, (ICINCO 2009) ISBN 978-989-674-002-3, pages 59-68. DOI: 10.5220/0002253900590068


in Bibtex Style

@conference{workshop anniip09,
author={Danniel Cavalcante Lopes and Rafael Marrocos Magalhães and Jorge Dantas de Melo and Adrião Duarte Dória Neto},
title={Implementation of a Modular Neural Network in a Multiple Processor System on Chip to Classify Electric Disturbance},
booktitle={Proceedings of the 5th International Workshop on Artificial Neural Networks and Intelligent Information Processing - Volume 1: Workshop ANNIIP, (ICINCO 2009)},
year={2009},
pages={59-68},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002253900590068},
isbn={978-989-674-002-3},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 5th International Workshop on Artificial Neural Networks and Intelligent Information Processing - Volume 1: Workshop ANNIIP, (ICINCO 2009)
TI - Implementation of a Modular Neural Network in a Multiple Processor System on Chip to Classify Electric Disturbance
SN - 978-989-674-002-3
AU - Cavalcante Lopes D.
AU - Marrocos Magalhães R.
AU - Dantas de Melo J.
AU - Dória Neto A.
PY - 2009
SP - 59
EP - 68
DO - 10.5220/0002253900590068