The Characterisation and Optimisation of TLC NAND Flash Memory using Machine Learning - A Position Paper

Sorcha Bennett, Joe Sullivan

2013

Abstract

Flash memory is non-volatile and, while it is becoming ever more commonplace, it is not yet a complete replacement for hard disk drives. The physical layout of Flash means that it is more susceptible to degradation over time, leading to a limited lifetime of use. This paper will give an introduction to NAND Flash memory, followed by an overview of the relevant research on the reliability of MLC memory, conducted using Machine Learning (ML). The results obtained will then be used to characterise and optimise the reliability of TLC memory.

References

  1. Aritome, S., Shirota, R., Hemink, G., Endoh, T., and Masuoka, F. (1993). Reliability issues of Flash memory cells. Proceedings of the IEEE, 81(5):776 -788.
  2. Bez, R., Camerlenghi, E., Modelli, A., and Visconti, A. (2003). Introduction to flash memory. Proceedings of the IEEE, 91(4):489 - 502.
  3. Cai, Y., Haratsch, E., Mutlu, O., and Mai, K. (2012). Error patterns in mlc nand flash memory: Measurement, characterization, and analysis. In Design, Automation Test in Europe Conference Exhibition (DATE), 2012, pages 521 -526.
  4. Compagnoni, C., Miccoli, C., Mottadelli, R., Beltrami, S., Ghidotti, M., Lacaita, A., Spinelli, A., and Visconti, A. (2010). Investigation of the threshold voltage instability after distributed cycling in nanoscale nand flash memory arrays. In Reliability Physics Symposium (IRPS), 2010 IEEE International, pages 604 - 610.
  5. Desnoyers, P. (2010). Empirical evaluation of nand flash memory performance. SIGOPS Oper. Syst. Rev., 44(1):50-54.
  6. Grupp, L., Caulfield, A., Coburn, J., Swanson, S., Yaakobi, E., Siegel, P., and Wolf, J. (2009). Characterizing flash memory: Anomalies, observations, and applications. In Microarchitecture, 2009. MICRO-42. 42nd Annual IEEE/ACM International Symposium on, pages 24 - 33.
  7. Hasler, P. and Lande, T. (2001). Overview of floatinggate devices, circuits, and systems. Circuits and Systems II: Analog and Digital Signal Processing, IEEE Transactions on, 48(1):1 -3.
  8. Hemink, G., Tanaka, T., Endoh, T., Aritome, S., and Shirota, R. (1995). Fast and accurate programming method for multi-level nand eeproms. In VLSI Technology, 1995. Digest of Technical Papers. 1995 Symposium on, pages 129 -130.
  9. Hogan, D., Arbuckle, T., and Ryan, C. (2012a). Evolving a storage block endurance classifier for flash memory: A trial implementation. Not yet published. Presented at 11th IEEE International Conference on Cybernetic Intelligent Systems 2012, University of Limerick, Limerick, Ireland.
  10. Hogan, D., Arbuckle, T., Ryan, C., and Sullivan, J. (2012b). Evolving a retention period classifier for use with flash memory. ECTA, Not yet published. To be published - in Proceedings of 4th International Conference on Evolutionary Computation Theory and Applications (ECTA 2012).
  11. IEEE (1998). Ieee standard definitions and characterization of floating gate semiconductor arrays. IEEE Std 1005- 1998. Endurance: Pg 86, Section 7.
  12. JEDEC (2011). Stress-Test-Driven Qualification of Integrated Circuits - JESD47H-01. Jedec Solid State Technology Association, Published by JEDEC Solid State Technology Association 2011 3103 North 10th Street, Suite 240 South Arlington, VA 22201.
  13. KonceptAnalytics (2010). Global flash memory market report - 2010 edition. Market Report SKU: KOAN2835768 48 Pages, MarketResearch.com. Accessed on: 11/10/2012.
  14. Koza, J. R. (1992). Genetic Programming: On the Programming of Computers by Means of Natural Selection. Number ISBN 0-262-11170-5. The MIT Press, Available from: The MIT Press.
  15. Lee, S. S. (2011). Emerging challenges in nand flash technology. Keynote 6, page 4. Flash Product Planning Group, Hynix Semiconductor Inc., Flash Memory Summit.
  16. Micheloni, R., Marelli, A., and Ravasio, R. (1998). Error Correction Codes for Non-Volatile Memories, volume XII. Springer.
  17. Pavan, P., Bez, R., Olivo, P., and Zanoni, E. (1997). Flash memory cells-an overview. Proceedings of the IEEE, 85(8):1248 -1271.
  18. Suh, K.-D., Suh, B.-H., Um, Y.-H., Kim, J.-K., Choi, Y.- J., Koh, Y.-N., Lee, S.-S., Kwon, S.-C., Choi, B.-S., Yum, J.-S., Choi, J.-H., Kim, J.-R., and Lim, H.-K. (1995). A 3.3 v 32 mb nand flash memory with incremental step pulse programming scheme. In SolidState Circuits Conference, 1995. Digest of Technical Papers. 41st ISSCC, 1995 IEEE International, pages 128 -129, 350.
  19. Sullivan, J. and Ryan, C. (2007). A destructive evolutionary algorithm process. In Frontiers in the Convergence of Bioscience and Information Technologies, 2007. FBIT 2007, pages 761 -764.
  20. Tanaka, T., Tanzawa, T., and Takeuchi, K. (1997). A 3.4- mbyte/sec programming 3-level nand flash memory saving 40size per bit. Technical Report 4-93081 3-76- X, Symposium on VLSl Circuits Digest of Technical Papers. Pages 65 - 66.
  21. Tewksbury, S. K. and Brewer, J. E. (2008). Nonvolatile Memory Technologies with Emphasis on Flash. IEEE Press Series on Microelectronic Systems. IEEE Press Series, 445 Hoes Lane, Piscataway, NJ 08854.
  22. Yaakobi, E., Grupp, L., Siegel, P., Swanson, S., and Wolf, J. (2012). Characterization and error-correcting codes for tlc flash memories.
  23. Yaakobi, E., Ma, J., Grupp, L., Siegel, P., Swanson, S., and Wolf, J. (2010). Error characterization and coding schemes for Flash memories. In GLOBECOM Workshops (GC Wkshps), 2010 IEEE, pages 1856 -1860.
Download


Paper Citation


in Harvard Style

Bennett S. and Sullivan J. (2013). The Characterisation and Optimisation of TLC NAND Flash Memory using Machine Learning - A Position Paper . In Proceedings of the 5th International Conference on Agents and Artificial Intelligence - Volume 2: ICAART, ISBN 978-989-8565-39-6, pages 559-564. DOI: 10.5220/0004330305590564


in Bibtex Style

@conference{icaart13,
author={Sorcha Bennett and Joe Sullivan},
title={The Characterisation and Optimisation of TLC NAND Flash Memory using Machine Learning - A Position Paper},
booktitle={Proceedings of the 5th International Conference on Agents and Artificial Intelligence - Volume 2: ICAART,},
year={2013},
pages={559-564},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0004330305590564},
isbn={978-989-8565-39-6},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 5th International Conference on Agents and Artificial Intelligence - Volume 2: ICAART,
TI - The Characterisation and Optimisation of TLC NAND Flash Memory using Machine Learning - A Position Paper
SN - 978-989-8565-39-6
AU - Bennett S.
AU - Sullivan J.
PY - 2013
SP - 559
EP - 564
DO - 10.5220/0004330305590564