Systematic Design of Real-Time Systems Based on CSP+T Process Algebra

Manuel I. Capel, José R. Balsas, Juan A. Holgado

Abstract

In this paper, a bottom-up formal technique to obtain a correct system specification from the RT/SA requirements specification of real-time systems is proposed. As an application, a design of the production cell is introduced.

References

  1. Baresi, L., Pezze, M.:Towards Formalising Structural Analisis. ACM Transactions on Software Engineering and Methodology, 7, 1998, 1, pp.80-107.
  2. Capel, M.I.: Mathematical Modeling of Technical Processes, Informatech, Košice, 2000, pp.59-81. ISBN: 80-88941-12-1.
  3. Fencott, P.C., Galloway, A.J., Lockyer, M.A., O'Brien, S.J., Pearson, S.: Formalising the Semantics of Ward-Mellor SA/RT Essential Models Using Process Algebra. In FME'94: Industrial Benefit of Formal Methods. LNCS 873, Springer-Verlag, 1994, pp.681-702.
  4. ŽIC, J.J.: Time-Constrained Buffer Specifications in CSP+T and Timed CSP. ACM Transactions on Programming Languages and Systems, 16, 1994, 6, pp.1661-1674.
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Paper Citation


in Harvard Style

I. Capel M., R. Balsas J. and A. Holgado J. (2004). Systematic Design of Real-Time Systems Based on CSP+T Process Algebra . In Proceedings of the 2nd International Workshop on Verification and Validation of Enterprise Information Systems - Volume 1: VVEIS, (ICEIS 2004) ISBN 972-8865-03-1, pages 81-83. DOI: 10.5220/0002684700810083


in Bibtex Style

@conference{vveis04,
author={Manuel I. Capel and José R. Balsas and Juan A. Holgado},
title={Systematic Design of Real-Time Systems Based on CSP+T Process Algebra},
booktitle={Proceedings of the 2nd International Workshop on Verification and Validation of Enterprise Information Systems - Volume 1: VVEIS, (ICEIS 2004)},
year={2004},
pages={81-83},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002684700810083},
isbn={972-8865-03-1},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 2nd International Workshop on Verification and Validation of Enterprise Information Systems - Volume 1: VVEIS, (ICEIS 2004)
TI - Systematic Design of Real-Time Systems Based on CSP+T Process Algebra
SN - 972-8865-03-1
AU - I. Capel M.
AU - R. Balsas J.
AU - A. Holgado J.
PY - 2004
SP - 81
EP - 83
DO - 10.5220/0002684700810083