REALIZATION AND OPTIMIZATION OF H.264 DECODER FOR DUAL-CORE SOC

Jia-Ming Chen, Chiu-Ling Chen, Jian-Liang Luo, Po-Wen Cheng, Chia-Hao Yu, Shau-Yin Tseng, Wei-Kuan Shih

Abstract

This paper presents an H.264/AVC decoder realization on a dual-core SoC (System-on-Chip) platform by the well-designed macroblock level software partitioning. Furthermore, optimizations of the procedures executed on each core, and data movement between two cores are captured from software and hardware techniques. The evaluation results show that a video with D1 (720×480 pixels) resolution can reach real-time decoding by the implementation, which provides a valuable experience for similar designs.

References

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Paper Citation


in Harvard Style

Chen J., Chen C., Luo J., Cheng P., Yu C., Tseng S. and Shih W. (2007). REALIZATION AND OPTIMIZATION OF H.264 DECODER FOR DUAL-CORE SOC . In Proceedings of the Second International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2007) ISBN 978-989-8111-13-5, pages 305-312. DOI: 10.5220/0002138403050312


in Bibtex Style

@conference{sigmap07,
author={Jia-Ming Chen and Chiu-Ling Chen and Jian-Liang Luo and Po-Wen Cheng and Chia-Hao Yu and Shau-Yin Tseng and Wei-Kuan Shih},
title={REALIZATION AND OPTIMIZATION OF H.264 DECODER FOR DUAL-CORE SOC},
booktitle={Proceedings of the Second International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2007)},
year={2007},
pages={305-312},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002138403050312},
isbn={978-989-8111-13-5},
}


in EndNote Style

TY - CONF
JO - Proceedings of the Second International Conference on Signal Processing and Multimedia Applications - Volume 1: SIGMAP, (ICETE 2007)
TI - REALIZATION AND OPTIMIZATION OF H.264 DECODER FOR DUAL-CORE SOC
SN - 978-989-8111-13-5
AU - Chen J.
AU - Chen C.
AU - Luo J.
AU - Cheng P.
AU - Yu C.
AU - Tseng S.
AU - Shih W.
PY - 2007
SP - 305
EP - 312
DO - 10.5220/0002138403050312