A PARAMETERIZABLE HANDEL-C NEURAL NETWORK IMPLEMENTATION FOR FPGA

Cherrad Benbouchama, Mohamed Tadjine, Ahmed Bouridane

Abstract

This paper shows the design possibility of a parameterizable implementation of neural multi-layer network on FPGA circuits (Field Programmable Gate Array) through the use of Handel-C language. The algorithm used for the training is the back-propagation. The tools of implementation and synthesis are the DK 4 of Celoxica and the ISE 6.3 of Xilinx. The targeted components are XCV2000 on Celoxica RC1000 board and XC2V1000 on RC200. The representation of the real numbers in fixed point was used for the data processing. The realization of the activation function is made with the approximate polynomial. A high level environment was designed in order to specify and introduce architecture parameters.

References

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Paper Citation


in Harvard Style

Benbouchama C., Tadjine M. and Bouridane A. (2009). A PARAMETERIZABLE HANDEL-C NEURAL NETWORK IMPLEMENTATION FOR FPGA . In Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO, ISBN 978-989-8111-99-9, pages 325-328. DOI: 10.5220/0002166903250328


in Bibtex Style

@conference{icinco09,
author={Cherrad Benbouchama and Mohamed Tadjine and Ahmed Bouridane},
title={A PARAMETERIZABLE HANDEL-C NEURAL NETWORK IMPLEMENTATION FOR FPGA},
booktitle={Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO,},
year={2009},
pages={325-328},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002166903250328},
isbn={978-989-8111-99-9},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO,
TI - A PARAMETERIZABLE HANDEL-C NEURAL NETWORK IMPLEMENTATION FOR FPGA
SN - 978-989-8111-99-9
AU - Benbouchama C.
AU - Tadjine M.
AU - Bouridane A.
PY - 2009
SP - 325
EP - 328
DO - 10.5220/0002166903250328