MULTI-CORE COMPUTING UNIT FOR ARTIFICIAL NEURAL NETWORKS IN FPGA CHIP

Marek Bohrn, Lukas Fujcik

Abstract

This article describes a design and features of a multi-core unit for performing computing operations required for artificial neural network functioning. Its purpose is to speed up computing operations of the neural network. The number of computing cores can be altered as needed to achieve the required performance. VHDL language has been used to build this module. It has been optimized for the Spartan-3 family FPGA chips from Xilinx. These chips are favorable because of their low price and a high number of on-chip multipliers and block memory units. Spartan-3 chips facilitate parallel computing operations within neural networks to a very high level and thus help to achieve high computing power.

References

  1. Ohomondi, Amos, R., Rajapasake, Jagath, C., 2006. FPGA Implementations of Neural Networks, Springer Netherlands
  2. Fausett, L., 1994. Fundamentals of Neural Networks, Prentice Hall New Jersey
  3. Masters, T., 1993. Practical Neural Network Recipes in C++, Academic Press California
  4. Xilinx, 2006. Spartan-3 FPGA Family: Complete Data Sheet, Xilinx company
  5. Suhap, S., Becerikili, Y., Yazici, S., 2006. Neural Network Implementation in Hardware Using PFGAs, 13th International Conference, ICONIP 2006, SpringerVerlag Germany
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Paper Citation


in Harvard Style

Bohrn M. and Fujcik L. (2009). MULTI-CORE COMPUTING UNIT FOR ARTIFICIAL NEURAL NETWORKS IN FPGA CHIP . In Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO, ISBN 978-989-8111-99-9, pages 149-152. DOI: 10.5220/0002172101490152


in Bibtex Style

@conference{icinco09,
author={Marek Bohrn and Lukas Fujcik},
title={MULTI-CORE COMPUTING UNIT FOR ARTIFICIAL NEURAL NETWORKS IN FPGA CHIP},
booktitle={Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO,},
year={2009},
pages={149-152},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002172101490152},
isbn={978-989-8111-99-9},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO,
TI - MULTI-CORE COMPUTING UNIT FOR ARTIFICIAL NEURAL NETWORKS IN FPGA CHIP
SN - 978-989-8111-99-9
AU - Bohrn M.
AU - Fujcik L.
PY - 2009
SP - 149
EP - 152
DO - 10.5220/0002172101490152