PARISIAN APPROACH - Reducing Computational Effort to Improve SMT Performance by setting Resizable Caches

Josefa Díaz, Francisco Fernández de Vega, J. Ignacio Hidalgo, Oscar Garnica

Abstract

Evolutionay Algorithm are techniques widely used in the resolution of complex problems. On the other hand, Simultaneous Multithreading improves the throughput of the processor core taking advantage of Instruction Level Parallelism and Thread Level Parallelism. In this environment adaptation the cache configuration, at runtime according to workloads settings will be improved the processor performance. This improvement is achieved by using resizable caches. In a previous work, we proposed a Genetic Algorithm to find the better cache configurations according to the needs and characteristics of the workloads. However the computational cost needed for the evaluation process is very high. In this paper we propose the use of the Parisian Evolution Approach to improve dynamically reconfigurable cache designs, and reduce the computational cost associated. We study the behavior of a set of benchmarks, taking into account their needs over cache memory hierarchy in each phase of execution, in order to adapt the cache configuration and to increase the number of instructions per cycle. Experimental results show a large saving in computing time and some improvement on the instructions per cycle achieved in previous approaches.

References

  1. Collet, P., Lutton, E., Raynal, F., and Schoenauer, M. (2000). Polar ifs + parisian genetic programming = efficient ifs inverse problem solving. Genetic Programming and Evolvable Machines, pages 339-361.
  2. Díaz, J., Hidalgo, J. I., Fernández, F., Garnica, O., and L ópez, S. (2009). Improving smt performance: an application of genetic algorithms to configure resizable caches. Proc. of the 11th Annual Conf. Companion on Genetic and Evolutionary Computation Conf.: Late Breaking Papers, pages 2029-2034.
  3. Dropsho, S., Buyuktosunoglu, A., Balasubramonian, R., Albonesi, D., Dwarkadas, S., Semeraro, G., Magklis, G., and Scott, M. (2002). Integrating adaptive on-chip storage structures for reduced dynamic power. In In proc. 11th Int'l. Conf. on Parallel Architectures and Compilation techniques, pages 141-152.
  4. Holland, J. (1975). Adaptation in Natural and Artificial Systems. University of Michigan Press.
  5. L ópez, S., Dropsho, S., Albonesi, D., Garnica, O., and Lanchares, J. (2007). Rate-driven control of resizable caches for highly threaded smt processors. In 16th Int'l. Conf. on Parallel Architecture and Compilation Techniques(PACT 2007), page 416.
  6. Olague, G., Dunn, E., and Lutton, E. (2008). Individual Evolution as an Adaptive Strategy for Photogrammetric Network Design.
  7. Tullsen, D. M., Eggers, S. J., Levy, H. M., Emer, J. S., Lo, J. L., and Stamm, R. L. (1996). Exploiting choice: Instruction fetch and issue on an implementable simultaneous multithreading processor. In Proc. 23rd Int'l Sump. on Computer Architecture, pages 191-202.
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Paper Citation


in Harvard Style

Díaz J., Fernández de Vega F., Ignacio Hidalgo J. and Garnica O. (2010). PARISIAN APPROACH - Reducing Computational Effort to Improve SMT Performance by setting Resizable Caches . In Proceedings of the International Conference on Evolutionary Computation - Volume 1: ICEC, (IJCCI 2010) ISBN 978-989-8425-31-7, pages 275-280. DOI: 10.5220/0003113702750280


in Bibtex Style

@conference{icec10,
author={Josefa Díaz and Francisco Fernández de Vega and J. Ignacio Hidalgo and Oscar Garnica},
title={PARISIAN APPROACH - Reducing Computational Effort to Improve SMT Performance by setting Resizable Caches},
booktitle={Proceedings of the International Conference on Evolutionary Computation - Volume 1: ICEC, (IJCCI 2010)},
year={2010},
pages={275-280},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003113702750280},
isbn={978-989-8425-31-7},
}


in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Evolutionary Computation - Volume 1: ICEC, (IJCCI 2010)
TI - PARISIAN APPROACH - Reducing Computational Effort to Improve SMT Performance by setting Resizable Caches
SN - 978-989-8425-31-7
AU - Díaz J.
AU - Fernández de Vega F.
AU - Ignacio Hidalgo J.
AU - Garnica O.
PY - 2010
SP - 275
EP - 280
DO - 10.5220/0003113702750280