DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA

Sumedh Attarde, Siddharth Joshi, Yash Deshpande, Sunil Puranik, Sachin Patkar

Abstract

In this paper, we present the design of an embedded system performing double precision sparse matrix vector multiplication (SpMxV), a key scientific computation kernel in iterative solvers, for very large matrices (millions of rows). The embedded system is implemented using the Xilinx MicroBlaze platform on the XUPV5-LX110T FPGA development board. Due to their size, matrices generally encountered in scientific computation need to be stored on off-chip DRAMs. A novel processing paradigm involving blocking of the matrix, and a novel data access mechanism which pre-fetches required data in bursts from off-chip DRAMS to hide large DRAM random access latencies are proposed and implemented. The processing element has been implemented as a prototype accelerator peripheral in an embedded system for the iterative Gauss-Jacobi algorithm.

References

  1. Bell, N. and Garland, M. (2008). Efficient sparse matrixvector multiplication on CUDA. NVIDIA Technical Report NVR-2008-004, NVIDIA Corporation.
  2. Davis, T. and Yu, H. (2010). The university of florida sparse matrix collection. http://www.cise.ufl.edu/research/ sparse/matrices/.
  3. deLorimier, M. and DeHon, A. (2005). Floating-point sparse matrix-vector multiplication for fpgas. FPGA 2005: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, pages 75-85.
  4. Golub, G. H. and Loan, C. F. V. (1996). Matrix Computations. Johns Hopkins University Press, 3 edition.
  5. (2007). Fpga based sparse matrix vector multiplication using commodity dram memory. FPL, pages 786-791.
  6. Kuzmanov, G. and Taouil, M. (2009). Reconfigurable sparse/dense matrix-vector multiplier. Proceedings of the International Conference FPT 2009, pages 483- 488.
  7. Morris, G. R. and Prasanna, V. (2007). Sparse matrix computations on reconfigurable hardware. Computer, vol 40, no 3, pages 58-64.
  8. Morris, G. R., Prasanna, V. K., and Anderson, R. D. (2006). A hybrid approach for mapping conjugate gradient onto an fpga-augmented reconfigurable supercomputer. FCCM 7806: Proceedings of the 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, pages 3-12.
  9. Sun, J., Peterson, G., and O.O, S. (2007). Mapping sparse matrix-vector multiplication on fpgas. Proc. Reconfigurable Systems Summer Inst. (RSSI).
  10. Williams, S., Oliker, L., Vuduc, R., Shalf, J., Yelick, K., and Demmel, J. (2007). Optimization of sparse matrixvector multiplication on emerging multicore platforms. SC 7807: Proceedings of the 2007 ACM/IEEE conference on Supercomputing, pages 1-12.
  11. Zhuo, L. and Prasanna, V. (2005). Sparse matrix-vector multiplication on fpgas. FPGA 2005: Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, pages 63-74.
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Paper Citation


in Harvard Style

Attarde S., Joshi S., Deshpande Y., Puranik S. and Patkar S. (2011). DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA . In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-8425-48-5, pages 476-484. DOI: 10.5220/0003400804760484


in Bibtex Style

@conference{peccs11,
author={Sumedh Attarde and Siddharth Joshi and Yash Deshpande and Sunil Puranik and Sachin Patkar},
title={DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA},
booktitle={Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2011},
pages={476-484},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003400804760484},
isbn={978-989-8425-48-5},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA
SN - 978-989-8425-48-5
AU - Attarde S.
AU - Joshi S.
AU - Deshpande Y.
AU - Puranik S.
AU - Patkar S.
PY - 2011
SP - 476
EP - 484
DO - 10.5220/0003400804760484