ADDRESSING THE HARDWARE RESOURCE REQUIREMENTS OF NETWORK-ON-CHIP BASED NEURAL ARCHITECTURES

Sandeep Pande, Fearghal Morgan, Seamus Cowley, Brian Mc Ginley, Jim Harkin, Snaider Carrillo, Liam Mc Daid

Abstract

Network on Chip (NoC) based Spiking Neural Network (SNN) hardware architectures have been proposed as embedded computing systems for data/pattern classification and control applications. As the NoC communication infrastructure is fully reconfigurable, scaling of these systems requires large amounts of distributed on-chip memory for storage of the SNN synaptic connectivity (topology) information. This large memory requirement poses a serious bottleneck for compact embedded hardware SNN implementations. The goal of this work is to reduce the topology memory requirement of embedded hardware SNNs by exploring the combination of fixed and configurable interconnect through the use of fixed sized clusters of neurons and NoC communication infrastructure. This paper proposes a novel two-layered SNN structure as a neural computing element within each neural tile. This architectural arrangement reduces the SNN topology memory requirement by 50%, compared to a non-clustered (single neuron per neural tile) SNN implementation. The paper also proposes sharing of the SNN topology memory between neural cluster outputs within each neural tile, for utilising the on-chip memory efficiently. The paper presents hardware resource requirements of the proposed architecture by mapping SNN topologies with random and irregular connectivity patterns (typical of practical SNNs). The architectural scheme of sharing the SNN topology memory between neural cluster outputs, results in efficient utilisation of the SNN topology memory and helps accommodate larger SNN applications on the proposed architecture. Results illustrate up to a 66% reduction in the required silicon area of the proposed clustered neural tile SNN architecture using shared topology memory compared to the non-clustered, non-shared memory architecture.

References

  1. Benini, L. & De Micheli, G., 2002. Networks on chips: a new SoC paradigm. Computer, 35(1), pp.70-78.
  2. Cawley, Seamus et al., 2011. Hardware spiking neural network prototyping and application. Genetic Programming and Evolvable Machines.
  3. Ehrlich, M. et al., 2007. Wafer-scale VLSI implementations of pulse coupled neural networks. In Proceedings of the International Conference on Sensors, Circuits and Instrumentation Systems.
  4. Emery, R., Yakovlev, A. & Chester, G., 2009. Connection-centric network for spiking neural networks. In Networks-on-Chip, 2009. NoCS 2009. 3rd ACM/IEEE International Symposium on. Networks-on-Chip, 2009.
  5. Furber, S. & Brown, A., 2009. Biologically-Inspired Massively-Parallel Architectures - Computing Beyond a Million Processors. In Application of Concurrency to System Design, 2009. ACSD 7809
  6. Furber, S., Temple, S. & Brown, A., 2006. On-chip and inter-chip networks for modeling large-scale neural systems. In Circuits and Systems, 2006. ISCAS 2006. Proceedings. 2006 IEEE International Symposium on. Circuits and Systems, 2006.
  7. Gerstner, W. & Kistler, W. M., 2002. Spiking neuron models, Cambridge University Press.
  8. Glackin, B. et al., 2005. A Novel Approach for the Implementation of Large Scale Spiking Neural Networks on FPGA Hardware. In Computational Intelligence and Bioinspired Systems. pp. 552-563.
  9. Harkin, Jim, Morgan, Fearghal, McDaid, Liam, Hall, Steve, et al., 2009. A reconfigurable and biologically inspired paradigm for computation using network-onchip and spiking neural networks. Int. J. Reconfig. Comput., 2009, pp.1-13.
  10. Kohl, N. & Miikkulainen, R., 2008. Evolving neural networks for fractured domains. In Proceedings of the 10th annual conference on Genetic and evolutionary computation. GECCO 7808. New York, NY, USA: ACM, p. 1405-1412.
  11. Maass, W., 1997. Networks of spiking neurons: The third generation of neural network models. Neural Networks, 10(9), pp.1659-1671.
  12. Maguire, L. P., McGinnity, T. M., Glackin, B., et al., 2007. Challenges for large-scale implementations of spiking neural networks on FPGAs. Neurocomputing, 71(1-3), pp.13-29.
  13. Marrow, P., 2000. Nature-Inspired Computing Technology and Applications. BT Technology Journal, 18(4), pp.13-23.
  14. Morgan, F., Cawley, S., Harkin, J., Mc, B., Ginley, L.M.D., et al., 2009. An Evolvable NoC-Based Spiking Neural Network Architecture.
  15. Morgan, F., Cawley, S., McGinley, B., et al., 2009. Exploring the evolution of NoC-based Spiking Neural Networks on FPGAs. In Field-Programmable Technology, 2009. FPT 2009.
  16. Morgan, Fearghal, Cawley, Seamus, McGinley, Brian, Pande, Sandeep, McDaid, Liam, Glackin, Brendan, et al., 2009. Exploring the Evolution of NoC-Based Spiking Neural Networks on FPGAs.
  17. Pande, Sandeep, Morgan, Fearghal, Cawley, Seamus, McGinley, Brian, Carrillo, S., Harkin, Jim, et al., 2010. EMBRACE-SysC for analysis of NoC-based Spiking Neural Network architectures. In System on Chip (SoC), 2010 International Symposium on. System on Chip (SoC), 2010
  18. Pearson, M. J. et al., 2007. Implementing Spiking Neural Networks for Real-Time Signal-Processing and Control Applications: A Model-Validated FPGA Approach. Neural Networks, IEEE Transactions on, 18(5), pp.1472-1487.
  19. Ros, E., Ortigosa, E. M., et al., 2006. Real-time computing platform for spiking neurons (RT-spike). Neural Networks, IEEE Transactions on, 17(4), pp.1050- 1063.
  20. Schemmel, J., Fieres, J. & Meier, K., 2008. Wafer-scale integration of analog neural networks. In Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence).
  21. Upegui, A., Peña-Reyes, C. A. & Sanchez, E., 2005. An FPGA platform for on-line topology exploration of spiking neural networks. Microprocessors and Microsystems, 29(5), pp.211-223.
  22. Vainbrand, D. & Ginosar, R., 2010. Network-on-chip architectures for neural networks. Microprocessors and Microsystems, In Press, Uncorrected Proof, p.-.
  23. Vogelstein, R. J. et al., 2007. Dynamically Reconfigurable Silicon Array of Spiking Neurons With ConductanceBased Synapses. Neural Networks, IEEE Transactions on, 18(1), pp.253-265.
  24. Yajie Chen et al., 2006. A Solid State Neuron for the Realisation of Highly Scaleable Third Generation Neural Networks. In Solid-State and Integrated Circuit Technology, 2006. ICSICT 7806. 8th International Conference on. Solid-State and Integrated Circuit Technology, 2006.
  25. Yajie Chen et al., 2008. A programmable facilitating synapse device. In Neural Networks, 2008. IJCNN 2008. (IEEE World Congress on Computational Intelligence). IEEE International Joint Conference on. Neural Networks, 2008. IJCNN 2008.
Download


Paper Citation


in Harvard Style

Pande S., Morgan F., Cowley S., Mc Ginley B., Harkin J., Carrillo S. and Mc Daid L. (2011). ADDRESSING THE HARDWARE RESOURCE REQUIREMENTS OF NETWORK-ON-CHIP BASED NEURAL ARCHITECTURES . In Proceedings of the International Conference on Neural Computation Theory and Applications - Volume 1: NCTA, (IJCCI 2011) ISBN 978-989-8425-84-3, pages 128-137. DOI: 10.5220/0003676601280137


in Bibtex Style

@conference{ncta11,
author={Sandeep Pande and Fearghal Morgan and Seamus Cowley and Brian Mc Ginley and Jim Harkin and Snaider Carrillo and Liam Mc Daid},
title={ADDRESSING THE HARDWARE RESOURCE REQUIREMENTS OF NETWORK-ON-CHIP BASED NEURAL ARCHITECTURES},
booktitle={Proceedings of the International Conference on Neural Computation Theory and Applications - Volume 1: NCTA, (IJCCI 2011)},
year={2011},
pages={128-137},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003676601280137},
isbn={978-989-8425-84-3},
}


in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Neural Computation Theory and Applications - Volume 1: NCTA, (IJCCI 2011)
TI - ADDRESSING THE HARDWARE RESOURCE REQUIREMENTS OF NETWORK-ON-CHIP BASED NEURAL ARCHITECTURES
SN - 978-989-8425-84-3
AU - Pande S.
AU - Morgan F.
AU - Cowley S.
AU - Mc Ginley B.
AU - Harkin J.
AU - Carrillo S.
AU - Mc Daid L.
PY - 2011
SP - 128
EP - 137
DO - 10.5220/0003676601280137