A PIPELINED BASED FPGA IMPLEMENTATION OF A GENETIC ALGORITHM

Nonel Thirer

Abstract

Many problems common to the electrical and electronics field can be solved by finding a target function and its minimum or maximum. For such problems, usually an analytical solution is not implementable, and therefore iterative algorithms are used. One such efficient algorithm is the Genetic Algorithm (GA). The GA imitates the biological evolution process, finding the solution by implementing the “natural selection” principle, which asserts that the strong has higher chances to survive. The GA is an iterative procedure which operates on a population of individuals called "chromosomes" or "possible solutions" (usually represented by a binary code) and performs several processes on the population individuals, in order to produce a new population - the same as in the biological evolution. Using the algorithm on large populations requires substantial hardware resources. Also, naturally, the amount of time necessary to reach a solution increases, due to the greater number of iterations needed. In this paper, we present an FPGA pipelined based method designed to implement a GA, which provides a high-speed solution for large populations, with a minimum of resources. This outcome is obtained by a procedure which operates sequentially with parts of the population. In addition, an immigration unit is defined to provide an efficient communication between these parts in different iterations. Moreover, some possible solutions to improve our method are analyzed.

References

  1. M. Affenzeller A. O., 2009. Genetic Algorithms and Genetic Programming - Modern Concepts and Practical Applications, CRC Press, USA.
  2. N. Nedjah, L. M. Mourelle, 2007. An efficient problemindependent hardware implementation of genetic algorithms., Neurocomputing 71, p.88-94.
  3. Mao F. So, Angus Wu, 1999. FPGA Implementation of Four -Step Genetic Search Algorithm., Electronics, Circuits and Systems, Proc. of ICECS 7899, vol.2 p.11 43-1146.
  4. Tatshuito Tachibana A. O., 2006. Flexible Implementation of Genetic Algorithms on FPGA, Proc. of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, FPGA, USA, February 22-24, 2006, 9 pages
  5. Tiago Carvalho Oliveira, Valfredo Pilla Jr, 2004. An Implementation of Compact Genetic Algorithm on FPGA for extrinsic evolvable Hardware, IEEE Transactions on Evolutionary Computation, p.1143-1146.
  6. Godkin Andrey, Nonel Thirer, 2010. A FPGA Implementation of Hardware Based Accelerator for a Genetic Algorithm, Proc. of IEEE 26-th Conv. of Electrical and Electronics Engineers in Israel, p.578- 580.
Download


Paper Citation


in Harvard Style

Thirer N. (2011). A PIPELINED BASED FPGA IMPLEMENTATION OF A GENETIC ALGORITHM . In Proceedings of the International Conference on Evolutionary Computation Theory and Applications - Volume 1: ECTA, (IJCCI 2011) ISBN 978-989-8425-83-6, pages 343-345. DOI: 10.5220/0003687703430345


in Bibtex Style

@conference{ecta11,
author={Nonel Thirer},
title={A PIPELINED BASED FPGA IMPLEMENTATION OF A GENETIC ALGORITHM},
booktitle={Proceedings of the International Conference on Evolutionary Computation Theory and Applications - Volume 1: ECTA, (IJCCI 2011)},
year={2011},
pages={343-345},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003687703430345},
isbn={978-989-8425-83-6},
}


in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Evolutionary Computation Theory and Applications - Volume 1: ECTA, (IJCCI 2011)
TI - A PIPELINED BASED FPGA IMPLEMENTATION OF A GENETIC ALGORITHM
SN - 978-989-8425-83-6
AU - Thirer N.
PY - 2011
SP - 343
EP - 345
DO - 10.5220/0003687703430345