EFFICIENT DESIGN OF BIT-LEVEL ACCELERATOR ARCHITECTURES FOR THE DEDR-RASF REMOTE SENSING ALGORITHM USING SUPER-SYSTOLIC ARRAYS

A. Castillo Atoche, J. Estrada Lopez, L. Rizo Dominguez, R. Quijano Cetina

Abstract

In this paper, we propose bit-level hardware accelerator architectures for real time implementation of large-scale remote sensing (RS) imaging. The computational complex RS operations of the DEDR-RASF algorithm are implemented in efficient bit-level high-throughput accelerators units. Super-Systolic Arrays (SSAs) and High Performance Embedded Computing (HPEC) techniques were used in aggregation with a HW/SW co-design scheme, achieving the required real-time data processing for newer RS applications. The bit-level SSA accelerators were implemented in a Virtex 5 XC5VFX130T Field Programable Gate Array (FPGA) technology. Performance results revels the significant improvement in both area and time metrics over previous works.

References

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Paper Citation


in Harvard Style

Castillo Atoche A., Estrada Lopez J., Rizo Dominguez L. and Quijano Cetina R. (2012). EFFICIENT DESIGN OF BIT-LEVEL ACCELERATOR ARCHITECTURES FOR THE DEDR-RASF REMOTE SENSING ALGORITHM USING SUPER-SYSTOLIC ARRAYS . In Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-8565-00-6, pages 327-333. DOI: 10.5220/0003835203270333


in Bibtex Style

@conference{peccs12,
author={A. Castillo Atoche and J. Estrada Lopez and L. Rizo Dominguez and R. Quijano Cetina},
title={EFFICIENT DESIGN OF BIT-LEVEL ACCELERATOR ARCHITECTURES FOR THE DEDR-RASF REMOTE SENSING ALGORITHM USING SUPER-SYSTOLIC ARRAYS},
booktitle={Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2012},
pages={327-333},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003835203270333},
isbn={978-989-8565-00-6},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - EFFICIENT DESIGN OF BIT-LEVEL ACCELERATOR ARCHITECTURES FOR THE DEDR-RASF REMOTE SENSING ALGORITHM USING SUPER-SYSTOLIC ARRAYS
SN - 978-989-8565-00-6
AU - Castillo Atoche A.
AU - Estrada Lopez J.
AU - Rizo Dominguez L.
AU - Quijano Cetina R.
PY - 2012
SP - 327
EP - 333
DO - 10.5220/0003835203270333