High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach

George S. Athanasiou, Chara I. Chalkou, D. Bardis, Harris E. Michail, George Theodoridis, Costas E. Goutis

Abstract

Hash functions are exploited by many cryptographic primitives that are incorporated in crucial cryptographic schemes and commercial security protocols. Nowadays, there is an active international competition, launched by the National Institute of Standards and Technology (NIST), for establishing the new hash standard, SHA-3. One of the semi-finalists is the JH algorithm. In this paper, two high throughput hardware architectures of the complete JH algorithm are presented. The difference between them is the existence of 3 pipeline stages at the second one. They both are designed to support all the possible versions of the algorithm and are implemented in Xilinx Virtex-4, Virtex-5, and Virtex-6 FPGAs. Based on the experimental results, the proposed architectures outperform the existing ones in terms of Throughput/Area factor, regarding all FPGA platforms and JH algorithm’s versions.

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Paper Citation


in Harvard Style

S. Athanasiou G., I. Chalkou C., Bardis D., E. Michail H., Theodoridis G. and E. Goutis C. (2012). High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach . In Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2012) ISBN 978-989-8565-24-2, pages 126-135. DOI: 10.5220/0004049801260135


in Bibtex Style

@conference{secrypt12,
author={George S. Athanasiou and Chara I. Chalkou and D. Bardis and Harris E. Michail and George Theodoridis and Costas E. Goutis},
title={High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach},
booktitle={Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2012)},
year={2012},
pages={126-135},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0004049801260135},
isbn={978-989-8565-24-2},
}


in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2012)
TI - High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach
SN - 978-989-8565-24-2
AU - S. Athanasiou G.
AU - I. Chalkou C.
AU - Bardis D.
AU - E. Michail H.
AU - Theodoridis G.
AU - E. Goutis C.
PY - 2012
SP - 126
EP - 135
DO - 10.5220/0004049801260135