On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function

Harris E. Michail, George S. Athanasiou, Andreas Gregoriades, George Theodoridis, Costas E. Goutis

Abstract

Hash functions are among the major blocks of modern security schemes, used in many applications to provide authentication services. To meet the applications’ real-time constraints, they are implemented in hardware offering high-performance and increased security solutions. However, faults occurred during their operation result in the collapse of the authentication procedure, especially when they are used in security-critical applications such as military or space ones. In this paper, a Totally Self-Checking (TSC) design is introduced for the currently most-used hash function, namely the SHA-1. A detailed description concerning the TSC development of the data- and control-path is provided. To the best of authors’ knowledge, it is the first time that a TSC hashing core is presented. The proposed design has been implemented in 0.18μm CMOS technology and experiments on fault caverage, performance, and area have been performed. It achieves 100% coverage in the case of odd erroneous bits. The same coverage is also achieved for even erroneous bits, if they are appropriately spread. Compared to the corresponding Duplicated-with-Checking (DWC) design, the proposed one is more area-efficient by almost 15% keeping the same frequency.

References

  1. Ahmad, D., I., Das, A., S., 2007. Analysis and detection of errors in implementation of SHA-512 algorithms on FPGAs. In Int. Journal of computer Oxford University Publishing,, vol.50, no.6, pp.728-738.
  2. Anderson, D., A., 1971. Design of Self-Checking Digital Networks Using Coding Techniques. Doctoral Dissertation. CSL/Univ. Illinois, Urbana, rep. n.527.
  3. Bertoni, G., Breveglieri, L., Koren, I., Piuri, V., 2003. Error analysis and Detection Procedures for Hardware Implementation of the Advance Encryption Standard. In Computers, IEEE Transactions on , vol.52, no.4, pp. 492- 505.
  4. Juliato, T., M., Gebotys, C., 2008. SEU-resistant SHA-256 designs for Security Satellites. In 10th Workshop on Signal Processing for Space Communications (SPSC) Conference, pp.1-17. Greece, EU.
  5. Juliato, T., M., Gebotys, C., 2010. An efficient faulttolerance technique for the Keyed-Hash Message Authentication Code. In International Conference on Aerospace, IEEE, pp.1-17. Big Sky, MT.
  6. Karri, R., Wu, K., Mishra, P., Kim, Yongkook, 2001. Fault-Based Side-Channel Cryptanalysis Tolerant Rijndael Symmetric Block Cipher Architecture. In International Symposium on Defect and Fault Tolerance in VLSI Systems. pp.427-435. San Francisco, CA, USA.
  7. Karri, R., Wu, K., Mishra, P., Kim, Y., 2002. , Concurrent Error Detection Schemes for Fault Based SideChannel Cryptanalysis of Symmetric Block Ciphers. In Computer-Aided Design of Integrated Circuits and Systems (CAD), IEEE Transactions on, vol.21, no.12, pp. 1509- 1517.
  8. Lala, P., K., 2001. Self-Checking and Fault Tolerant Digital Design. Morgan Kaufman Publishers. San Francisco, USA.
  9. Loeb, L., 1998. Secure Electronic Transactions: Introduction and Technical Reference. Artech House Publishers. Norwood, USA.
  10. Loshin, P., 2004. IPv6: Theory, Protocol and Practice, Elsevier Publications. USA.
  11. NIST, 2001. Introduction to Public Key Technology and the Federal PKI Infrastructure. SP 800-32., NIST, US Department of Commerce Publications, USA.
  12. NIST, 2002a. Digital Signature Standard Federal Information Processing Standard. FIPS 186-1 NIST, Department of Commerce Publications, USA.
  13. NIST, 2002b. The Keyed-Hash message authentication code (HMAC). NIST-FIPS 198, NIST, US Department of Commerce Publications, USA.
  14. NIST, 2005. Guide to IPSec VPN's. NIST-SP800-77, NIST, Department of Commerce Publications, USA.
  15. NIST), 2008. Secure Hash Standard (SHS). NIST-FIPS 180-3, Department of Commerce Publications, USA.
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Paper Citation


in Harvard Style

E. Michail H., S. Athanasiou G., Gregoriades A., Theodoridis G. and E. Goutis C. (2012). On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function . In Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2012) ISBN 978-989-8565-24-2, pages 270-275. DOI: 10.5220/0004059302700275


in Bibtex Style

@conference{secrypt12,
author={Harris E. Michail and George S. Athanasiou and Andreas Gregoriades and George Theodoridis and Costas E. Goutis},
title={On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function},
booktitle={Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2012)},
year={2012},
pages={270-275},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0004059302700275},
isbn={978-989-8565-24-2},
}


in EndNote Style

TY - CONF
JO - Proceedings of the International Conference on Security and Cryptography - Volume 1: SECRYPT, (ICETE 2012)
TI - On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function
SN - 978-989-8565-24-2
AU - E. Michail H.
AU - S. Athanasiou G.
AU - Gregoriades A.
AU - Theodoridis G.
AU - E. Goutis C.
PY - 2012
SP - 270
EP - 275
DO - 10.5220/0004059302700275