Appropriate Multi-core Architecture for Safety-critical Aerospace Applications - Certifiable Real-time Switching Network

Stephan C. Stilkerich, Christian Siemers, Christian Ristig

2014

Abstract

The continues improvement of aircraft’s as well as the steady optimization of the overall air traffic during the last decade increased the demand for processing power in the aircraft and on ground, simultaneously. Multi-Core platforms could offer the demanded processing power and form factor, but today’s multi-core components are principally not usable for any safety critical industry and especially not usable for the avionic domain, because these components are optimized for average case performance and not for full fledged predictability. This is especially true for the inter-core communicaton network. We argue that a regular and low overhead Beneš-Network communication structure between the cores and between the cores and the shared resources, can smoothly pave the way for certification of multi-core architectures in the avionic domain. The presented details on the regular structure of the network, the scheduling variants discussed in the paper and the currently on-going research work to proof profound theoretical limits, bounds etc. substantiate our claim for an utilization of multi-cores in the avionic domain and with respect to the valid regulations for airborne equipment.

References

  1. Aust, S. (2013). Ein Echtzeit-Parallelrechner zur Rezentralisierung von Steuergerten in Automobilen. PhD thesis University of Clausthal, Clausthal-Zellerfeld Germany.
  2. Aust, S. and Richter, H. (October 2012). Real-time processor interconnection network for fpga-based multiprocessor system-on-chip (mpsoc). In 4th International Conference on Advanced Engineering Computing and Applications in Sciences; ADVCOMP 2010, Florenz, Italy.
  3. Aust, S. and Richter, H. (September 2010). Space division of processing power for feed forward and feed back control in complex production and packaging machinery. In World Automation Congress; WAC 2010, Kobe, Japan.
  4. Newman, P. (1988). Fast Packet Switching for Integrated Services. PhD thesis University of Cambridge, Cambridge, UK.
  5. Stilkerich, S. C. (May 2013). Multicore systems in the light of aerospace safety regulations. In 8th MultiCore Developers Conference, San Jose, USA.
  6. Waldherr, S., Knust, S., and Aust, S. (2013). Message Scheduling for Real-Time Interprocessor Communication. to be published.
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Paper Citation


in Harvard Style

C. Stilkerich S., Siemers C. and Ristig C. (2014). Appropriate Multi-core Architecture for Safety-critical Aerospace Applications - Certifiable Real-time Switching Network . In Proceedings of the 4th International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-758-000-0, pages 180-185. DOI: 10.5220/0004801901800185


in Bibtex Style

@conference{peccs14,
author={Stephan C. Stilkerich and Christian Siemers and Christian Ristig},
title={Appropriate Multi-core Architecture for Safety-critical Aerospace Applications - Certifiable Real-time Switching Network},
booktitle={Proceedings of the 4th International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2014},
pages={180-185},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0004801901800185},
isbn={978-989-758-000-0},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 4th International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - Appropriate Multi-core Architecture for Safety-critical Aerospace Applications - Certifiable Real-time Switching Network
SN - 978-989-758-000-0
AU - C. Stilkerich S.
AU - Siemers C.
AU - Ristig C.
PY - 2014
SP - 180
EP - 185
DO - 10.5220/0004801901800185