Design of a Real Coded GA Processor

A. Tsukahara, A. Kanasugi

Abstract

Real Coded Genetic Algorithm (RCGA) has been attracting attention as one of the GA for handling real-valued vectors. Various GA hardware have been proposed, for evolvable hardware, and for an increase in computational throughput. Yet, there are few reports of RCGA hardware. Herein, we propose a design for a real coded GA processor. The proposed processor is implemented using the JGG (Just Generation Gap) as a generation alternation model and the REX (Real coded Ensemble Crossover) as a crossover. In addition, the evaluation functions that depend on problem are calculated using soft macro CPU. The proposed processor is to be applied expected in embedded field applications because of it can be implemented in one chip FPGA.

References

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Paper Citation


in Harvard Style

Tsukahara A. and Kanasugi A. (2015). Design of a Real Coded GA Processor . In Proceedings of the 7th International Joint Conference on Computational Intelligence - Volume 1: ECTA, ISBN 978-989-758-157-1, pages 334-339. DOI: 10.5220/0005631503340339


in Bibtex Style

@conference{ecta15,
author={A. Tsukahara and A. Kanasugi},
title={Design of a Real Coded GA Processor},
booktitle={Proceedings of the 7th International Joint Conference on Computational Intelligence - Volume 1: ECTA,},
year={2015},
pages={334-339},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0005631503340339},
isbn={978-989-758-157-1},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 7th International Joint Conference on Computational Intelligence - Volume 1: ECTA,
TI - Design of a Real Coded GA Processor
SN - 978-989-758-157-1
AU - Tsukahara A.
AU - Kanasugi A.
PY - 2015
SP - 334
EP - 339
DO - 10.5220/0005631503340339