Validation of Loop Parallelization and Loop Vectorization Transformations

Sudakshina Dutta, Dipankar Sarkar, Arvind Rawat, Kulwant Singh

Abstract

Loop parallelization and loop vectorization of array-intensive programs are two common transformations applied by parallelizing compilers to convert a sequential program into a parallel program. Validation of such transformations carried out by untrusted compilers are extremely useful. This paper proposes a novel algorithm for construction of the dependence graph of the generated parallel programs. The transformations are then validated by checking equivalence of the dependence graphs of the original sequential program and the parallel program using a standard and fairly general algorithm reported elsewhere in the literature. The above equivalence checker still works even when the above parallelizing transformations are preceded by various enabling transformations except for loop collapsing which changes the dimensions of the arrays. To address the issue, the present work expands the scope of the checker to handle this special case by informing it of the correspondence between the index spaces of the corresponding arrays in the sequential and the parallel programs. The augmented algorithm is able to validate a large class of static affine programs. The proposed methods are implemented and tested against a set of available benchmark programs which are parallelized by the polyhedral auto-parallelizer LooPo and the auto-vectorizer Scout. During experiments, a bug of the compiler LooPo on loop parallelization has been detected.

References

  1. Allen, J. R., Kennedy, K., Porterfield, C., and Warren, J. (1983). Conversion of control dependence to data dependence. In Proceedings of the 10th ACM SIGACTSIGPLAN Symposium on Principles of Programming Languages, POPL 7883, pages 177-189, New York, NY, USA. ACM.
  2. Bandyopadhyay, S., Banerjee, K., Sarkar, D., and Mandal, C. (2012). Translation validation for PRES+ models of parallel behaviours via an FSMD equivalence checker. In Progress in VLSI Design and Test - 16th International Symposium, VDAT 2012, Shibpur, India, July 1-4, 2012. Proceedings, pages 69-78.
  3. Collard, J.-F. and Griebl, M. (1997). Array dataflow analysis for explicitly parallel programs. Parallel Processing Letters, 07(02):117-131.
  4. Griebl, M. and Lengauer, C. (1996). The loop parallelizer loopo. In Proceedings of Sixth Workshop on Compilers for Parallel Computers, volume 21 of Konferenzen des Forschungszentrums Jlich, pages 311-320. Forschungszentrum.
  5. Karfa, C., Sarkar, D., Mandal, C., and Kumar, P. (2008). An equivalence-checking method for scheduling verification in high-level synthesis. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on, 27(3):556-569.
  6. Krinke, J. (1998). Static slicing of threaded programs. In Proceedings of the 1998 ACM SIGPLAN-SIGSOFT Workshop on Program Analysis for Software Tools and Engineering, PASTE 7898, pages 35-42, New York, NY, USA. ACM.
  7. Kundu, S., Lerner, S., and Gupta, R. K. (2010). Translation validation of high-level synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems, 29(4):566- 579.
  8. Padua, D. A. and Wolfe, M. J. (1986). Advanced compiler optimizations for supercomputers. Commun. ACM, 29(12):1184-1201.
  9. Pouchet, L. (2012). Polybench: The polyhedral benchmark suite. http://www-roc.inria.fr/pouchet/software/ polybench/download/.
  10. Shashidhar, K. C., Bruynooghe, M., Catthoor, F., and Janssens, G. (2005). Functional equivalence checking for verification of algebraic transformations on array-intensive source code. In Proceedings of Design, Automation and Test in Europe, 2005. Proceedings, pages 1310-1315 Vol. 2.
  11. Verdoolaege, S., Janssens, G., and Bruynooghe, M. (2012). Equivalence checking of static affine programs using widening to handle recurrences. ACM Trans. Program. Lang. Syst., 34(3):11:1-11:35.
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Paper Citation


in Harvard Style

Dutta S., Sarkar D., Rawat A. and Singh K. (2016). Validation of Loop Parallelization and Loop Vectorization Transformations . In Proceedings of the 11th International Conference on Evaluation of Novel Software Approaches to Software Engineering - Volume 1: ENASE, ISBN 978-989-758-189-2, pages 195-202. DOI: 10.5220/0005869501950202


in Bibtex Style

@conference{enase16,
author={Sudakshina Dutta and Dipankar Sarkar and Arvind Rawat and Kulwant Singh},
title={Validation of Loop Parallelization and Loop Vectorization Transformations},
booktitle={Proceedings of the 11th International Conference on Evaluation of Novel Software Approaches to Software Engineering - Volume 1: ENASE,},
year={2016},
pages={195-202},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0005869501950202},
isbn={978-989-758-189-2},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 11th International Conference on Evaluation of Novel Software Approaches to Software Engineering - Volume 1: ENASE,
TI - Validation of Loop Parallelization and Loop Vectorization Transformations
SN - 978-989-758-189-2
AU - Dutta S.
AU - Sarkar D.
AU - Rawat A.
AU - Singh K.
PY - 2016
SP - 195
EP - 202
DO - 10.5220/0005869501950202