Authors:
Naima Armaoui
;
Mohamed Naija
and
Samir Ben Ahmed
Affiliation:
Laboratory of Computer for Industrial Systems, INSAT, Tunis and Tunisia
Keyword(s):
Real-time & Embedded Systems, MPSoC, Co-modeling, MARTE, Reconfiguration, Performance Estimation.
Related
Ontology
Subjects/Areas/Topics:
Biomedical Engineering
;
Biomedical Signal Processing
;
Real-Time Systems
Abstract:
The development of Multi-Processor System-on-Chip (MPSoC) for high-performance embedded applications has become a major challenge for designers due to a number of crucial constraints to meet, such as functional correctness and temporal performance. This paper presents a new process intended to support and facilitate the co-design and scheduling analysis of high-performance applications on MPSoCs. The contribution of this process is that it is designed to i) model the system functionality, execution architectures and allocation of software and hardware parts using a high-level modeling language ii) verify scheduling analysis of the system using a simulation tool and iii) offer a reconfiguration technique in order to meet constraints and preserve the system non-functional properties (NFPs). As a proof of concepts, we present a case study consisting of a JPEG encoder, with very promising results.