New Solutions for Optimal Hardware Tests of Reconﬁgurable Hardware

Systems

Asma Ben Ahmed

1,2

, Olfa Mosbahi

and Mohamed Khalgui

LISI Laboratory, National Institute of Applied Sciences and Technology , University of Carthage, Carthage, Tunisia

Tunisia Polytechnic School, University of Carthage, Carthage, Tunisia

Keywords:

Embedded System, Reconﬁguration, Hardware Veriﬁcation, Testing, Fault Collapsing, Optimization.

Abstract:

This research paper deals with Reconﬁgurable Hardware Systems (abbreviated, RHS) that should be adapted to

their environment under well-deﬁned conditions. A reconﬁguration scenario is a run-time hardware operation

allowing the addition/removal of hardware components. We classify the reconﬁguration scenarios into three

levels: Architectural, Structural and Data Reconﬁguration Levels. We propose a new solution for optimal

hardware tests of RHS based on the deﬁnition of new fault collapsing relationships termed Inter-Equivalence,

Inter-Dominance and Redundancy.

1 INTRODUCTION

In recent years, embedded systems have become ubiq-

uitous at a fast rate. An embedded system is a com-

puting machine designed for speciﬁc functions within

a larger system. Embedded systems often require

stringent performance, energy efﬁciency and ﬂexi-

bility for multifunctional use. In order to cope ef-

fectively and timely with these requirements, recon-

ﬁguration of system components at different levels

of abstraction has become a crucial task to change

systems during their execution while preserving their

availability. In the literature, we have two reconﬁg-

uration policies: static and dynamic reconﬁgurations

such as static reconﬁgurations applied off line (An-

gelov et al., 2005), dynamic reconﬁgurations are ap-

plied at run-time in two forms: manual reconﬁgura-

tions applied by users (Rooker et al., 2007) and au-

tomatic reconﬁgurations applied by intelligent agents

(Khalgui, 2010). The reconﬁguration can touch the

software level (Gharbi et al., 2010) and the underly-

ing hardware (Ahmadinia, 2007) .

Reconﬁgurable Hardware System (RHS) allows

post-fabrication conﬁgurability, enabling single base

hardware design to implement a variety of circuitries.

Furthermore, it permits the system to transform the

underlying hardware to be adapted to temporal re-

quirements of an application when internal or exter-

nal changes occur. The quality and the correctness

of hardware parts are greatest concerns in embedded

systems. Hardware veriﬁcation such that hardware

testing ensures that the hardware components con-

tains no defects that could affect the products correct

functioning (Steininger, 2000).

One approach for considerably reducing the cost

of the testing process is fault collapsing. Fault col-

lapsing is the process of generating a reduced fault

set in a circuit using the Equivalence and the Dom-

inance relationships and is classiﬁed as structural or

functional (Prasad et al., 2002). These techniques can

be said Intra-Equivalence and Intra-Dominance fault

collapsing as well as they are interested in faults lo-

cated at the same circuit.

For RHS, the number of faults can become very

large. Our problem consists in reducing the hardware

test cost of reconﬁgurable system. It is thus bene-

ﬁcial to minimize the set of faults whenever possi-

ble. Greater reduction is possible by deﬁning new

techniques reducing faults from different circuits of

the device under test. Our proposition is original and

different from all others since no one proposes hard-

ware tests for RHS. In this research work, we propose

a new solution for optimal hardware tests of RHS.

The hardware test is addressed at the gate level and

we consider the single stuck-at fault model. We de-

ﬁne the RHS as a network of components intercon-

nected via signals. To address all possible forms of

reconﬁguration, we classify the reconﬁguration sce-

narios into three levels: the ﬁrst level deals with addi-

tion/removal of gates. The second deals with activa-

tion/deactivation of internal signals between already

used components and the third consists in selecting

281

Ben Ahmed A., Mosbahi O. and Khalgui M..

New Solutions for Optimal Hardware Tests of Reconﬁgurable Hardware Systems.

DOI: 10.5220/0005243902810288

In Proceedings of the 5th International Conference on Pervasive and Embedded Computing and Communication Systems (PECCS-2015), pages

281-288

ISBN: 978-989-758-084-0

 2015 SCITEPRESS (Science and Technology Publications, Lda.)

data via a multiplexer. For the purpose of optimiz-

ing both the set of faults for the RHS and the set of

test vectors for the test generation process, we pro-

pose new fault collapsing relationships termed Inter-

Equivalence, Inter-Dominance and Redundancy re-

ducing faults from different circuits of the RHS. Our

experiments show that the size of collapsed fault set

is reduced to just 8 faults for an initial collapsed fault

set of 108 faults, when the Inter-circuits relations are

considered. With the traditional relations, we obtain

63 faults. Therefore, the number of faults to be con-

sidered in test generation and fault diagnostic can be

decreased considerably, so the overall run-time can be

reduced.

The rest of this paper is organized as follows. Next

section is devoted to the background. Section 3 in-

troduces the case study. Section 4 presents the for-

malization of RHS while section 5 describes the new

characterization of faults in RHS. Section 6 shows the

implementation. Finally, section 7 presents the con-

clusion.

2 BACKGROUND

In hardware testing, physical defects are abstracted

into logical fault model. In fact, many fault mod-

els have been proposed such as stuck-at faults, bridg-

ing faults, delay fault models, etc (Abramovici and

Menon, 1997). The most widely used model is the

single stuck-at fault (Al-Asaad and Lee, 2002). To

test a circuit under a given fault model, a set of input

vectors is applied to the inputs of the circuit. Then,

the output responses are compared with the fault-free

responses to determine whether the circuit is faulty.

Circuits that fail to produce correct responses are as-

sumed to be faulty. An input vector is said to be a test

vector if it produces a different output response from

that of the fault-free circuit. Consequently, we have

for an input vector, V, to be a test vector:

(V ) ⊕ f

(V )=1

where f

is the fault-free function and f

is the faulty

function.

We present the gate level single stuck-at fault

model that will be used in this paper. Two properties

characterize a single stuck at fault, (i) just one line is

faulty (ii) the faulty line is permanently set to constant

logic value, either logic 0 or 1, referred to as stuck-at-

0 (Line/0) or stuck-at-1 (Line/1), respectively. Under

this model, the number of single stuck-at faults as-

sociated with each gate is twice the total number of

inputs and outputs of the gates.

Fault collapsing reduces the number of faults using

two relationships among faults: fault Equivalence and

fault Dominance.

Equivalence fault collapsing: Two faults f

and f

in a circuit C are said to be equivalent (i) if the cor-

responding faulty output of the circuits C

and C

respectively, are identical for every input vector ap-

plied to the circuit (ii) therefore f

and f

have exactly

the same set of test vectors. Hence, the set of vectors

that detect f

, can also detect f

. Consequently, if C

is simulated then C

has not to be simulated (Veneris

et al., 2004).

Dominance fault collapsing: A fault f

is said to

dominate a fault f

if all tests that detect f

also de-

tect f

, but detecting f

does not mean that f

is also

detected (Sethuram et al., 2008).

Note that no one treated the problem of fault col-

lapsing for a RHS. All related works are interested

in deﬁning faults located at the same circuit. No

relationships among faults of different circuits were

given.

3 CASE STUDY

We present, in this section, a case study to expose our

problem and to be assumed in the following as a run-

ning example. Let we assume a system with different

behaviors. The system is considered as reconﬁgurable

offering different services and implemented with dif-

ferent logics. Let C

, C

, . . . , C

, be combina-

tional logic circuits with primary inputs, S

, S

and one output Z

, with 1 ≤ i ≤ 10. We assume

that the 10 circuits are constructed using gates AND,

NAND, OR, NOR and XOR. Each circuit C

imple-

ments a logic function, as shown in ﬁgure 1.

Figure 1: Logic functions implementing the system.

Assuming that each circuit C

implements a re-

conﬁguration scenario characterized by correspond-

ing gates, signals and data. In order to make the sys-

tem ﬂexible, we propose to group these circuits in a

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single basic design where each circuit can be executed

at a given time when a corresponding reconﬁguration

is applied. In fact, to apply a hardware reconﬁgura-

tion, a multiplexer should be attached to the design

such as writing a new set of values into the input se-

lection reconﬁgures the hardware to implement a dif-

ferent circuit as shown in Figure 2.

Figure 2: The proposed system.

Let F = { f

, f

, . . . , f

} be the initial fault list

that contains all possible stuck-at faults for the pro-

posed system. According to the proposed case study,

the initial set of faults F contains 108 faults. The au-

thors propose in (Agrawal et al., 2003) a fault col-

lapsing using two relationships among faults in one

circuit: fault equivalence and fault dominance. By ap-

plying these relationships, we can reduce the number

of faults about 58.3%. We obtain 63 faults.

When comparing faults from different circuits, re-

dundancy of faults is possible so that inter-circuits re-

lations among faults do exist. As the number of faults

has a strong inﬂuence on the costs which must be

paid for the test pattern generation, it is interesting

to identify inter-circuits relations and to generate an

optimum fault list and an optimum set of test vectors.

Therefore, new relations should be proposed. This pa-

per is original since it deals with reconﬁgurable sys-

tems, and deﬁnes new relations between faults in or-

der to optimize the test process.

4 CONTRIBUTION:

RECONFIGURABLE

HARDWARE SYSTEM RHS

In our research, we are interested in Reconﬁgurable

Hardware Systems that we denote by RHS in the fol-

lowing. RHS is considered as a network of gates inter-

connected via signals and expressed in terms of data.

A hardware reconﬁguration will be any operation al-

lowing the activation (addition) and deactivation (re-

moval) of hardware components at run-time. There-

fore, at a given time (t), a change may affect the gates,

the signals or the input data. In order to switch from

a reconﬁguration to another, a multiplexer is attached

to the system such that multiplexer inputs present the

different circuits implementing the different reconﬁg-

urations. Assigning new values into the selector pins

reconﬁgures the system to implement a different cir-

cuit. To address all possible forms of reconﬁgura-

tion, we deﬁne three levels: (i) Architectural recon-

ﬁguration triggered by creating, deleting or updating

gates, (ii) Structural reconﬁguration allowing activa-

tion/deactivation of internal signals between already

used components, (iii) Data reconﬁguration allowing

selection of data via a multiplexer. This original clas-

siﬁcation covers all possible forms of reconﬁgurations

to dynamically change the behavior of an RHS de-

pending on the modiﬁcations that occurred in its en-

vironment.

In order to control the increasing complexity of

the RHS and to cover all forms of reconﬁguration, a

hierarchical design is becoming more and more im-

portant. We propose a design with three levels of hi-

erarchy: the top level is the architecture, the second

level is the structure and the third level presents data.

1) Architectural Reconﬁguration: consists in trans-

forming an architecture into another one at the same

level of abstraction. Such reconﬁguration is applied

by the addition and/ or the removal of gates.

Running Example 1:

According to the case study, the change from C

represents an architectural reconﬁguration sce-

nario occurred by the removal of gates AND and

OR and the addition of gates NOR and NAND. We

switch from C

to C

by the addition of the XOR

gate (see Figure 3).

2) Structural Reconﬁguration: modiﬁes the struc-

tural level by the activation or the deactivation of sig-

nals between already used gates as shown in Figure 4.

We keep the same gates but the signals between gates

are modiﬁed.

NewSolutionsforOptimalHardwareTestsofReconfigurableHardwareSystems

283

Figure 3: Architectural reconﬁguration.

Running example 2:

Through the example given in Figure 4, we notice

that AND and OR gates are retained. Z

and Z

are

expressed as follows: Z

; Z

+ S

Figure 4: Structural reconﬁguration.

3) Data reconﬁguration: consists in adding a mul-

tiplexer (data selector) in order to express the system

differently.

Figure 5: Data reconﬁguration.

RHS is deﬁned by the set of triples α, β and ϕ as

follows:

RHS ={α, β, ϕ } where α = {{components}}, β =

{{Signals}} and ϕ = {{Data}}.

At a given time (t), the system is characterized as

follows: RHS(t) = {X, Y, Z}, where X ∈ α ; Y ∈ β ; Z

∈ ϕ. X, Y and Z are respectively the set of gates, the

set of signals and the data set that have to implement

the system at a given time (t).

Let Ω be the initial fault list that contains all stuck-at

faults of the proposed system. Ω is initially equal to

108 faults.

Running Example 3:

In the example shown in Figure 5 , if x=0 then Z

. if x=1 then Z

Running Example 4: Based on these scenar-

ios, the RHS example is composed of three

main architectures (Archi

, Archi

). Each

architecture comprises three different structures

Struct

i j

, with 1 ≤ i ≤ 3 ; 1 ≤ j ≤ 3. Each struc-

ture can be expressed in terms of S

, S

and S

in terms of S

depending on input selection values.

16-to-1 Multiplexer is added to our model in order

to enable reconﬁgurations. Each circuit present-

ing the inputs of 16-to-1 multiplexer is expressing

architectural, structural and data reconﬁguration.

For the totality of our system, we have 18 possible

reconﬁgurations as shown in Figure 6.

Figure 6: Reconﬁgurable Hardware System.

5 CONTRIBUTION: NEW

CHARACTERIZATION OF

FAULTS IN RHS

5.1 Classiﬁcation of Faults

We deﬁne three new relations between faults: fault

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Running Example 5:

Continuing from the running example n4, α, β and

ϕ can take the following values:

α = {{G

(11), G

(11), Mux

(11)}, {G

(12),

(12), Mux

}, {G

(13), G

(13), Mux

(13)},

(21), G

(21), Mux

(21)}, {G

(22), G

(22),

Mux

(22)}, {G

(23), G

(23), Mux

(23)},

(31), G

(31), Mux

(31)}, {G

(32),

(32), Mux

(32)}, {G

(33), G

(33),

Mux

(33)}}

β ={{S

, S

, Z

}, {S

, S

, Z

}, {S

, S

, Z

}, {S

, S

, Z

}, {S

, S

}, {S

, S

, Z

}, {S

, S

, Z

},{S

, S

, Z

},{S

, S

, Z

}}

ϕ= {{S

, S

}, {S

}}

Running Example 6:

Continuing from the previous running example,

we suppose that the composition Archi

-Struct

with x=0, initially, implements the RHS then we

have

RHS(t

) = {{G

, G

, Mux

}, {S

, S

}, {S

, S

}}.

At a given time t

, a change may affect the ar-

chitectural level. The Archi

-Struct

is deployed.

The RHS is expressed as follows:

RHS(t

) = {{G

, G

, Mux

}, {S

, S

, Z

}, {S

, S

}}.

At a given time t

, a structural reconﬁguration can

occur: Archi

-Struct

is deployed.

RHS(t

) = {{G

, G

, Mux

}, {S

, S

, Z

}, {S

, S

}}.

Note that just internal signals are modiﬁed.

At t

, if the selector input x switch from x=0 to

x=1 then a data reconﬁguration occurs.

RHS(t

) = {{G

, G

, Mux

}, {S

, S

, Z

}, {S

}}

Inter-Equivalence, fault Inter-Dominance and fault

Redundancy.

Deﬁnition 1: Fault Inter-Equivalence

Let V

and V

be two sets of vectors that detect, re-

spectively, f

and f

. Two faults f

and f

in different

circuits C

and C

are said to be Inter-Equivalent (i)

if they are detected by exactly the same set of vec-

tors V

= V

, (ii) the input-output logic behaviors of

and C

are not necessary identical. If two faults

and f

are Inter-Equivalent, then only one of these

faults, say f

, needs to be retained in the fault list.

Deﬁnition 2: Fault Inter-Dominance

Let f

and f

be two faults in different circuits C

and

. Let V

be the set of all the vectors that detect

the fault f

. Similarly, let V

be the set of the vec-

tors that detect the fault f

. The Fault f

is said to

Inter-Dominate the fault f

(i) if V

contains V

that

means V

⊂ V

, (ii) the vectors that detect f

do not

necessary imply identical values at the corresponding

faulty outputs of C

and C

. If a fault f

dominates

a fault f

, then each vector that detects f

detects f

Therefore, f

can be deleted from the fault list.

Deﬁnition 3: Fault Redundancy

A fault f

is called redundant in different circuits C

and C

(i) if it is located at the same primary signal

used by the circuits C

and C

. If the fault appears in

the circuit C

, then it will also appear at the same sig-

nal of C

(ii) if the fault is at an internal signal of the

circuit C

and the same signal is present in C

, then f

is said to be redundant in C

and C

when f

is detected

by the same set of vectors. From the Redundancy

fault set, only one fault can be retained to represent

all faults in the corresponding fault set.

5.2 Application to Case Study:

Minimization of Faults for RHS

Consider the proposed system shown in Figure 6. It

has a total of 108 single stuck-at faults that can be re-

duced to 63 faults if we use the Intra-Equivalence and

the Intra-Dominance relationships. All faults collaps-

ing results are shown in Table 1: the number of col-

lapsed faults and the Collapse Ratio are given. The

latter is deﬁned as (Bushnell, 2001):

Collapse Ratio =

seto f collapsed f aults

seto f all f aults

Table 1: Fault collapsing results.

Circuit name All faults

Number of collapsed faults

(Collapse Ratio)

Intra-Equivalence Intra-Dominance

Archi

-Struct

12 4(0.33) 2(0.16)

Archi

-Struct

12 4(0.33) 2(0.16)

Archi

-Struct

12 4(0.33) 2(0.16)

Archi

-Struct

12 2(0.16) 1(0.083)

Archi

-Struct

12 2(0.16) 1(0.083)

Archi

-Struct

12 2(0.16) 1(0.083)

Archi

-Struct

12 4(0.33) 2(0.16)

Archi

-Struct

12 4(0.33) 2(0.16)

Archi

-Struct

12 4(0.33) 2(0.16)

A collapse ratio around 0.4 is quite typical for

Intra-Equivalence and Dominance collapsing. How-

ever, considering Inter-circuits relationships, which is

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285

the main topic of this paper, may provide smaller

collapsed fault set.

Inter-circuits fault collapsing reduces the number

of faults using three relationships among faults: Inter-

Equivalence, Inter-Dominance and Redundancy. For

Archi

, when comparing faulty versions of Struct

Struct

and Struct

, faults S

/1(12) from Struct

and S

/1(13) from Struct

are dropped since they

are Inter-Equivalent to S

/1(11) and S

/1(11) , respec-

tively. Also, faults S

/0 (11), S

/0(12) and S

/0(13)

are dropped since they Inter-Dominate S

/0(12),

/0(11) and S

/1(11), respectively. Faults S

/0(12),

/1(12), S

/0(12), S

/1(12), S

/1(13), S

/0(13) and

/1(13), which are derived from primary signals,

are dropped since they are redundant in Struct

and

Struct

. The remaining faults for Struct

are thus

/0, S

/1, S

/0, S

/1. This set of faults cov-

ers all faults for Struct

. For Archi

-Struct

, only

the fault S

/0 remains. The same process is re-

peated for the other architectures. With respect to

the proposed model, our hierarchical approach to

fault collapsing is as follows: we ﬁrst look for Inter-

Equivalence, Inter-Dominance and Redundancy rela-

tionships among all faults of different structures of

the same architecture. This process is called Intra-

Architecture fault collapsing. The latter is then fol-

lowed by Inter-Architectures fault collapsing where

we look for Inter-Equivalence, Inter-Dominance and

Redundancy relationships among remaining faults of

different architectures. By applying the proposed ap-

proach, we obtain the following results as shown in

Tables 2, 3 and 4. The Tables present, respectively,

Intra-Architecture fault collapsing results for Archi

and ﬁnally Inter-Architectures fault collapsing results

Table 2: Intra-Architecture fault collapsing results for

Archi

Initial fault list For:

Archi

-Struct

={S

/0, S

/1, S

/0, S

/1,

/0, S

/1, S

/0, S

/1, S

/1}

Archi

-Struct

={S

/0, S

/1, S

/0, S

/1,

/0, S

/1, S

/0, S

/1, S

/1}

Archi

-Struct

={S

/0, S

/1, S

/0, S

/1,

/0, S

/1, S

/0, S

/1, S

/1}

Number of collapsed faults (Collapse Ratio)

Inter-

Equivalence

Inter-

Dominance

Redundancy

2(0.074) 0(0.0) 14(0.51)

Remaining faults:

Archi

-Struct

={S

/0, S

/1, S

/0, S

/1,

/0, S

/1, S

/0, S

/1, S

/1}

Archi

-Struct

={S

/1}

Archi

-Struct

={S

/1}

for Archi

-Archi

Table 3: Intra-Architecture fault collapsing results for

Archi

Initial fault list For:

Archi

-Struct

={S

/0, S

/1, S

/0, S

/1,

/0, S

/1}

Archi

-Struct

={S

/0, S

/1, S

/0,

/0, S

/1}

Archi

-Struct

={S

/0, S

/1, S

/0, S

/0,

/0, S

/1}

Number of collapsed faults (Collapse Ratio)

Inter-

Equivalence

Inter-

Dominance

Redundancy

4(0.22) 0(0.0) 8(0.44)

Remaining faults:

Archi

-Struct

={S

/0, S

/1, S

/0, S

/1,

/0, S

/1}

Archi

-Struct

={}

Archi

-Struct

={}

Table 4: Inter-Architectures fault collapsing results for

Archi

-Archi

Initial fault list For:

Archi

-Struct

={S

/0, S

/1, S

/0,

/1}

Archi

-Struct

={}

Archi

-Struct

={S

/0}

Archi

-Struct

={S

/0, S

/1, S

/0, S

/1,

/0, S

/1, S

/0, S

/1, S

/1}

Archi

-Struct

={S

/1}

Archi

-Struct

={S

/1}

Archi

-Struct

={S

/0, S

/1, S

/0, S

/1,

/0, S

/1}

Archi

-Struct

={}

Archi

-Struct

={}

Number of collapsed faults (Collapse Ratio)

Inter-

Equivalence

Inter-

Dominance

Redundancy

1(0.04) 5(0.21) 9(0.39)

Remaining faults:

Archi

-Struct

={S

/0, S

/1, S

/0,

/1}

Archi

-Struct

={}

Archi

-Struct

={S

/0}

Archi

-Struct

={S

/1}

Archi

-Struct

={}

Archi

-Struct

={}

Archi

-Struct

={S

/1}

Archi

-Struct

={}

Archi

-Struct

={}

The ﬁnal fault list is thus {S

/0(11), S

/1(11),

/1(11), S

/0(11), S

/1(11), S

/0(13), S

/1(21),

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/1(31)}. Hence, by using Inter-Circuits fault col-

lapsing we are able to reduce the number of faults

from 63 to 8. This is, in effect, a 0.87 reduction

from the Intra-collapsing fault list which is divided

between 0.63 for Intra-Architecture fault collapsing

and 0.23 for Inter-Architecture fault collapsing.

In the next section, we propose the algorithms for

Inter-Circuits fault collapsing.

6 IMPLEMENTATION

Based on the new deﬁnitions of fault collapsing, we

present in this section the proposed algorithms. Let

= { f

, f

, . . . , f

} be the set of possible faults

in circuit C

. We suppose that T

is the list of po-

sitions of input values that generate different outputs

from the corresponding responses of the fault-free cir-

cuit C

. T

is the corresponding fault positions of

fault f

. Let F

= { f

, f

, . . . , f

} be the set of

possible faults in circuit C

and T

is the list of posi-

tions of faults for circuit C

. Algorithm 1 is developed

in order to reduce the set of faults between two cir-

cuits C

and C

using the Inter-Equivalence relation.

We propose algorithm 2 to decrease the fault set using

the Inter-Dominance relationship. Finally, algorithm

3 presents fault collapsing through the Redundancy

relation.

7 CONCLUSION AND FUTURE

WORK

In this paper, we propose three new fault collapsing

relations reducing faults from different circuits of the

RHS: fault Inter-Equivalence, fault Inter-Dominance

and fault Redundancy. This new classiﬁcation of

faults reduces considerably the number of faults

which leads to optimize the set of vectors to be con-

sidered in the test generation. Consequently, we op-

timize the overall cost of the hardware test for the re-

conﬁgurable systems. In our future work, we plan to

continue our research with the Automatic Test Pattern

Generation (ATPG) for the RHS.

Algorithm 1: Inter Equivalence Fault Collapsing.

Inputs:

← { f

, f

,. . . , f

}

i = 1 . . . k : the set of faults in C

← {T

, T

,. . . , T

}

i = 1 . . . k : the list of positions of faults for C

← { f

, f

B j

,. . . , f

}

j = 1 . . . h : the set of faults in C

← {T

, T

B j

,. . . , T

}

j = 1 . . . h : the list of positions of faults for C

Inter equi← {equi list [line 1], equi list [line 2],. . . ,

equi list [line l]}; initially empty

Begin

For i = 1 . . . sizeof(T

)

For j = 1 . . . sizeof(T

)

if the elements in T

[i] are the same than

the elements in T

[j]

then add line in Inter equi

with F

[i]: top of the list [line]

[j]: end of the list [line]

Remove T

[j] from T

Remove F

[j] from F

End if

End For

End

Algorithm 2: Inter Dominance Fault Collapsing.

Inputs:

← { f

, f

,. . . , f

}

i = 1 . . . k : the set of faults in C

← {T

, T

,. . . , T

}

i = 1 . . . k : the list of positions of faults for C

← { f

, f

B j

,. . . , f

}

j = 1 . . . h : the set of faults in C

← {T

, T

B j

,. . . , T

}

j = 1 . . . h : the list of positions of faults for C

Inter dom← {dom list [line 1], dom list [line 2],. . . ,

dom list [line l]}; initially empty

Begin

For i = 1 . . . sizeof(T

)

For j = 1 . . . sizeof(T

)

if the elements in T

[i] ⊂ T

[j]

then add line in Inter dom

with F

[i]: top of the list [line]

[j]: end of the list [line]

Remove T

[j] from T

Remove F

[j] from F

End if

End For

End

NewSolutionsforOptimalHardwareTestsofReconfigurableHardwareSystems

287

Algorithm 3: Redundancy Fault Collapsing.

Inputs:

← { f

, f

,. . . , f

}

i = 1 . . . k : the set of faults in C

← {T

, T

,. . . , T

}

i = 1 . . . k : the list of positions of faults for C

← { f

, f

B j

,. . . , f

}

j = 1 . . . h : the set of faults in C

← {T

, T

B j

,. . . , T

}

j = 1 . . . h : the list of positions of faults for C

Redundancy List:initially empty

Begin

SignalsA ← Extract signals from F

where Sig-

nalsA[i]

is the corresponding signals used by F

[i]

SignalsB ← Extract signals from F

where SignalsB[j]

is the corresponding signals used by F

[j]

For i = 1 . . . sizeof(F

)

For j = 1 . . . sizeof(F

)

if F

[i] is the same than F

[j]

if the corresponding SignalsA[i] and SignalsB[j]

are the same primary signal

then add line in Redundancy List

with F

[i]: top of the list [line]

[j]: end of the list [line]

Remove T

[j] from T

Remove F

[j] from F

Remove SignalsB[j] from SignalB

else

if the elements in T

[i] are the same than

the elements in T

[j]

then add line in Redundancy

List

with F

[i]: top of the list [line]

[j]: end of the list [line]

Remove T

[j] from T

Remove F

[j] from F

Remove SignalsB[j] from SignalB

End if

End For

End

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