New Methodology for Feasible Reconﬁgurable Real-time

Network-on-Chip NoC

Imen Khemaissia

1,2

, Olfa Mosbahi

, Mohamed Khalgui

1,4

and Zhiwu Li

3,4

National Institute of Applied Sciences and Technology, INSAT, University of Carthage, Carthage, Tunisia

Faculty of Sciences, Tunis El-Manar University, Tunis, Tunisia

Institute of Systems Engineering, Macau University of Science and Technology, Taipa, Macau

School of Electro-Mechanical Engineering, Xidian University, Xian 710071, China

Keywords:

Embedded System, Reconﬁgurable MPSoC, Multi-agent, Real-time and Low-power Scheduling.

Abstract:

The current research paper is interested in ﬂexible reconﬁgurable real-time Network-on-Chip (NoC) in Mul-

tiprocessors System-on-Chip MPSoC architectures. A NoC is composed of several nodes where each one

consists of a processor and a router. The reconﬁguration of a processor is any operation that permits the

addition-removal-update of periodic dependent OS (Operating System) tasks that are sharing resources. For

two added dependent tasks assigned to different processors, a message is added automatically on the NoC.

After any reconﬁguration scenario, several real-time constraints cannot be satisﬁed since a task can miss its

deadline and a message can take a long time to arrive to its destination. In order to re-obtain the system feasibil-

ity, we propose a new approach that is called CRM (abrev. Cynapsys Reconﬁgurable MPSoC). A multi-agent

architecture based on a master/slave model is deﬁned where a slave agent is assigned to each node to control

its local feasibility after any reconﬁguration scenario, and a master is proposed for the whole architecture if

any perturbation occurs at run-time by proposing software or hardware solutions. A developed tool at LISI

laboratory and Cynapsys is implemented for a real case study in order to evaluate the paper’s contribution.

1 INTRODUCTION

Recently, the embedded systems are based on the MP-

SoC oriented technologies since they meet the re-

quired performance of various applications in indus-

try (Z.Hajduk and J.Sadolewski, 2015). An MPSoC

is a system-on-chip (SoC) which is composed of nu-

merous processors commonly dedicated for embed-

ded applications. Reducing the power consumption

becomes a major concern for the high-performance

and reliability of such systems. The MPSoC can be

adapted to its environment after any external/internal

events that allow to add, remove or update the sys-

tem tasks or messages to be exchanged between the

processors of the chip. A hardware reconﬁguration

allows the activation/deactivation of a processor of

the architecture. We found in the literature various

interesting research works which deal with reconﬁg-

urable real-time embedded systems (X. Wang and Li,

2011), (J. F. Zhang, 2015), (George and Courbin, ),

more speciﬁcally the reconﬁguration of MPSoC ar-

chitectures (P.K.F. Holzenspies, 2007), (A. Samahi,

2007). Note that various research works on low-

power execution of MPSoC architectures are found

in (H. Javaid and Parameswaran, 2011), (R. Ben Ati-

tallah and Blouin, 2013), (Salehi and Ejlali, 2015).

Multiple algorithms are dedicated to schedule the OS

tasks of embedded systems (N.Q. Wu and Li, 2015),

(Baker, 1991), (Chetto and Chetto, 1989) (Burns and

Wellings, 2001), (T.P.Baker, 1990), (Liu and Layland,

1973). Although all of them are interesting, no one in

the related works deals with the real-time reconﬁg-

uration of an MPSoC architecture under low-power

and low-memory constraints. This work is original

since there is no related work that treats the low-

power-reconﬁguration of MPSoC oriented applica-

tions implemented by periodic OS tasks/messages un-

der precedence constraints and with shared resources.

In this paper, we assume an MPSoC-based applica-

tion denoted in the following by RSys and composed

of n nodes such that each one gathers a processor and

a router. The different processors of RSys execute pe-

riodic OS tasks. They are assumed to be under prece-

dence constraints and with shared resources. We use

the well-known scheduling policy earliest deadline

ﬁrst (EDF) to schedule the tasks that implement the

Khemaissia, I., Mosbahi, O., Khalgui, M. and Li, Z.

New Methodology for Feasible Reconﬁgurable Real-Time Network-on-Chip NoC.

DOI: 10.5220/0005992002490257

In Proceedings of the 11th International Joint Conference on Software Technologies (ICSOFT 2016) - Volume 1: ICSOFT-EA, pages 249-257

ISBN: 978-989-758-194-6

249

different processors of RSys. The immediate priority

ceiling protocol IPCP (Burns and Wellings, 2001) is

utilized to deal with the precedence constraints of de-

pendent tasks. The initial system is considered as fea-

sible, i.e., the utilization of each processor is equal or

less than 1. Several messages will be added too after

the addition of tasks. After the application of succes-

sive reconﬁguration scenarios, RSys becomes infeasi-

ble. Also, a message can take a long time to arrive

to its destination. In order to resolve all these prob-

lems, a new approach called CRM (Cynapsys Recon-

ﬁgurable MPSoC) is developed at Cynapsys

which

is a professional company in the embedded technolo-

gies. Indeed, all the real-time and precedence con-

straints should be satisﬁed. We propose a multi-agent

architecture based on the master/slave model to han-

dle feasible reconﬁgurations of RSys. We propose two

types of agents: i) A master agent: Controls the whole

architecture of RSys after applying any reconﬁgura-

tion scenario. If it receives a disapproval from the

slave agent, then it proposes the modiﬁcation of real-

time parameters of tasks or their assignment to other

processors of the same MPSoC architecture, or also

the removal of some of them. ii) A slave agent: Is

deﬁned for each processor to inform the master agent

if the energy is increased or the real-time constraints

are violated. We choose to apply the paper’s contri-

bution to FPGA Stratix III and a tool is proposed to

handle all the services provided by the different in-

telligent agents. The remainder of the paper is orga-

nized as follows: the next Section reviews the related

works. Section 3 formalizes the reconﬁgurable MP-

SoC architectures followed by a case study. Section 4

proposes a methodology for a reconﬁgurable feasible

real-time application. The implementation, simula-

tion, and analysis are found in Section 5. Finally, the

last Section summarizes this work with the presenta-

tion of future works.

2 STATE OF THE ART

We expose and analyze several research works which

are related to the current contribution. Since this

paper addresses the reconﬁgurable feasible NoC in

adaptive MPSoC architectures, we start ﬁrst by pre-

senting the characteristics of MPSoC and NoC. Then

we review some interesting related papers dealing

with the real-time scheduling of OS tasks.

2.1 MPSoC and NoC Characteristics

The MPSoC uses diverse processors usually addres-

Cynapsys company: http://www.cynapsys.de/

sed to embedded applications. It is used by structure

that are composed of multiple heterogeneous process-

ing elements with particular services indicating the re-

quirement of the expected application area (J. Sepul-

veda and Strum, 2012). These architectures meet

the performance needs of many applications in dif-

ferent domains such as multimedia, telecommunica-

tion and network security. Because of their compar-

atively high performance, ﬂexibility, and power efﬁ-

ciency, the MPSoC is based on NoC solutions (Hans-

son and Goossens, 2007),(Stensgaard and Sparso,

2008), (F. Martinez Vallina and saniie, 2007). Net-

work on chip (NoC) is known as a new paradigm

assigned for the interconnections within a system on

chip (SoC) that presents a viable communication in-

frastructure (Bobda and Ahmadinia, 2005). Although

all of them are interesting, there is no related work

that deals with the real-time reconﬁgurable NoC in

MPSoC architectures under low-power constraints.

2.2 Real-time Scheduling

Several successful studies in the literature deal with

the real-time scheduling of OS tasks. The work in

(Liu and Layland, 1973) proposes the earliest dead-

line ﬁrst (EDF) and the rate monotonic (RM) to

schedule periodic tasks. The work in (Burns and

Wellings, 2001) presents the original priority ceiling

protocol OPCP and immediate priority ceiling proto-

col IPCP in order to solve the scheduling problem of

the tasks that share resources. The research work in

(T.P.Baker, 1990) proposes the stack resource policy

SRP that allows processes with different priorities to

share a single run-time stack. In this paper, we use

the EDF for the scheduling of periodic tasks since it

is optimal under some assumptions.

In summary, a lot of successful investigations have

been done in the domain of reconﬁgurable MPSoC-

based embedded technologies. None of the previous

works takes into account the feasibility at run-time of

NoC in an MPSoC architecture under real-time and

energy constraints.

3 RECONFIGURABLE MPSoC

RSys

In this section, we start by formalizing the reconﬁg-

urable MPSoC RSys before exposing a case study that

explains the the problem under consideration.

ICSOFT-EA 2016 - 11th International Conference on Software Engineering and Applications

250

3.1 Formalization

We assume that RSys consists of the

matrix N

i∗ j

of nodes, i.e., RSys =

1,1

1,2

,...,N

2,1

2,2

i, j

,...,N

l,c

} (i ∈ [1..l]

and j ∈ [1..c]) where l and c represent respec-

tively the numbers of the rows and columns of the

network on chip NoC that is used to connect all

the nodes of RSys (?). RSys is considered to be

reconﬁgurable and adapted to its environment by

adding/updating/removing OS tasks to/from the

processors. We assume that each node N

i, j

is com-

posed of: (a) Processor Pr

i, j

: Executes periodic OS

tasks τ

i, j,k

(i ∈ [1..l], j ∈ [1..c] and k ∈ [1..n

i, j

]) that

share resources and under precedence constraints,

(b) Router R

i, j

: Is responsible of the message’s

forwarding in the NoC. The latter has a buffer that

contains the list of messages to be added from a

source node to a destination one. We note that all

the processors of RSys share data in a global memory

According to Liu and Layland in (Liu and Lay-

land, 1973), each periodic task τ

i, j,k

(i ∈ [1..l], j ∈

[1..c] and k ∈ [1..n

i, j

]) may generate many jobs. It

is characterized by: a) Release time R

i, j,k

: The time

when a job starts its execution. If the tasks are syn-

chronous, i.e, R

i, j,k

= 0 b) Period T

i, j,k

: Is the regu-

lar inter-arrival time, c) Deadline D

i, j,k

: The absolute

deadline that is equal to the sum of the release time

and the relative deadline, d) WCET C

i, j,k

: the time

required to execute a job, and e) static priority S

i, j,k

The greatest static priority is equal to 1, i.e., S

= 1

represents τ

i, j,k

with the highest static priority. We

consider that the tasks of RSys are sharing resources

and are with precedence constraints. We assume that

i, j,k

= D

i, j,k

. Each task in RSys is characterized by

inclusion and exclusion sets accordingto user require-

ments respectively where:

• Inclusion

set

(τ

i, j,k

): the set of processors that can

handle the execution of τ

i, j,k

• Exlusion

set

(τ

i, j,k

): the set of processors that can-

not handle the execution of τ

i, j,k

According to (I. Khemaissia and Khalgui, 2014),

(Baker, 1991), the processor utilization of periodic

tasks that share resources is calculated as follows :

per

(Pr

i, j

) = (

i, j

∑

k=1

i, j,k

),∀k ∈ [1..n

i, j

] (1)

where B

i, j,k

is the blocking factor that is deﬁned as

the time to spend by a task with a higher priority

when blocked. It waits the termination of a task with

a lower priority. In this work, we assume that the

blocking factor B

i, j,k

is assumed to be equal to 1 or 0

(Baker, 1991). The EDF algorithm is used to schedule

the independent tasks. For the schedule of tasks that

share resources, we use the IPCP. The technique pro-

posed in (I. Khemaissia and Khalgui, 2014) (Chetto

and Chetto, 1989) is utilized to deal with the depen-

dent tasks. For example, let us deﬁne two dependant

tasks τ

i, j,e

and τ

i, j, f

such that τ

i, j,e

precedes τ

i, j, f

. The

deadlines of the tasks are attributed as follows:

if τ

i, j,e

precedes τ

i, j, f

then S

i, j,e

< S

i, j, f

. The deadline

i, j,e

is given by:

i, j,e

= min(D

i, j,e

,(D

i, j, f

−C

i, j,e

)) (2)

By using Eq. (2), the precedence constraints will be

satisﬁed. We note that the initial utilization of each

processor U

bef

is equal to:

bef

(Pr

i, j

) = U

per

(Pr

i, j

) (3)

According to (X. Wang and Zhou, 2015) (I. khemais-

sia and Bouzayen, 2014), the energy to be consumed

by a processor is proportional to the processor utiliza-

tion. It is given by:

i, j

∝ U

bef

(Pr

i, j

)

(4)

Let we assume a reconﬁguration scenario at a spe-

ciﬁc time t. A software reconﬁguration is applied

by adding or removing OS tasks and U

bef

increases

to be U

aft

. We assume that the source task τ

i, j,h

exchanges a message m

(τ

i, j,h

;τ

a,b,k

) with a target

task destination τ

a,b,k

. A message m

(τ

i, j,h

;τ

a,b,k

)

in (I. Khemaissia and Khalgui, 2014) is character-

ized by: (i) A size S

(τ

i, j,h

;τ

a,b,k

), (ii) A trans-

mission period T

(τ

i, j,h

;τ

a,b,k

), (iii) A deadline

(τ

i, j,h

;τ

a,b,k

), (iv) A Worst Case Transmission

Time WCTT

(τ

i, j,h

;τ

a,b,k

), and (v) A static pri-

ority SP

(τ

i, j,h

;τ

a,b,k

) where:

WCTT = S

(τ

i, j,h

;τ

a,b,k

)/debit

NoC

(5)

(τ

i, j,h

;τ

a,b,k

) = (D

a,b,k

− C

a,b,k

) (6)

In this work, we assume that after each addition of a

pair of tasks a new message is added automatically.

The purpose of this research is to seek the optimal

path between the source task and the destination one

under real-time constraints. According to (B.D. Bui

and Caccamo, 2005), the bus utilization is calculated

as follows:

bus

(τ

i, j,h

;τ

a,b,k

)) =

∑

p=1

(τ

i, j,h

;τ

a,b,k

)

(τ

i, j,h

;τ

a,b,k

)

(7)

Note that m is the messages number.

3.2 Case Study

The proposed approach in the current paper is applied

to an FPGA Stratix III (Z-A. Obaid and Hamidon,

New Methodology for Feasible Reconﬁgurable Real-Time Network-on-Chip NoC

251

2009). Thus, we illustrate RSys through a running

example in order to explain the proposed methodol-

ogy by using theoretical tasks. Suppose that a star-

tix FPGA board is composed three Nios II processors

1,1

, Pr

1,2

and Pr

2,1

. We deﬁne the NoC as the com-

munication architecture between the components of

the MPSoC. Initially, RSys does not miss its real-time

constraints and low-power properties. Table 1 lists

the parameters of the different processors. We assume

that its initial utilization U

per

(Pr

2,1

), U

per

(Pr

1,1

) and

per

(Pr

1,2

) is equal to 0.8, 0.55 and 0.7, respec-

tively, and all the tasks are released at the time R

= 0

with T

= D

. We consider that S(τ

) > S(τ

) and

S(τ

) < S(τ

). By using Eq. (2), D

, D

and

are equal to 16, 20, 25 and 40, respectively. The

utilization of each processor is equal to 0.8, 0.55 and

0.7, respectively. Then, the initial energy consump-

tion is 0.36, 0.30 and 0.49, respectively. Thus, the

whole initial system is feasible. We assume also that

the NoC can initially support all the added messages

since its utilization is equal to 0.8.

Table 1: Characteristics of the initial periodic tasks.

i, j

4 20 Pr

1,1

5 25 Pr

1,2

1 20 Pr

1,1

3 30 Pr

1,2

3 20 Pr

1,1

6 40 Pr

1,2

6 40 Pr

1,1

5 20 Pr

1,2

Figure 1: Initial scheduling of Pr

1,1

and Pr

1,2

Table 2: Characteristics of the initial periodic messages.

Messages C

m1(τ

,τ

) 3 30 m5(τ

,τ

) 1 10

m2(τ

,τ

) 2 20 m6(τ

,τ

) 5 25

m3(τ

,τ

) 2 20 m7(τ

,τ

) 3 30

m4(τ

,τ

) 2 20 m8(τ

,τ

) 2 20

Table 3 indicates the parameters of the added pe-

riodic tasks. Furthermore, we activate a new Nios

II processor Pr

2,1

. The processor utilization after

the addition of OS tasks U

aft

(Pr

1,1

), U

aft

(Pr

1,2

) and

aft

(Pr

2,1

) will be 1.05, 1.05 and 1.1, respectively.

We deduct that the system is infeasible since the pro-

cessor utilization of each processor exceeds 1. Also

the energy consumption increases to be 1.1, 1.1 and

1.21, respectively.

After the addition of several messages, the bus uti-

lization becomes equal to 1.2 and several messages

Table 3: Characteristics of the added periodic tasks.

SetInc(τ

i, j,k

)

4 10 Pr

1,1

, Pr

2,1

2 20 Pr

1,1

, Pr

1,2

4 40 Pr

1,1

, Pr

2,1

9 30 Pr

1,2

, Pr

2,1

4 20 Pr

1,2

, Pr

2,1

2 40 Pr

1,2

, Pr

2,1

Figure 2: Scheduling after a reconﬁguration scenario.

Table 4: Characteristics of the added periodic messages.

Messages C

m(τ

,τ

) 4 40 m(τ

,τ

) 2 20

m(τ

,τ

) 4 10 m(τ

,τ

) 3 30

m(τ

,τ

) 2 20 m(τ

,τ

) 2 10

m(τ

,τ

) 8 40 m(τ

,τ

) 3 10

cannot be supported by the NoC. Moreover, the mes-

sages take a long time to be routed. For that new soft-

ware solutions are proposed for the NoC feasibility.

In the sections below, we propose new technical

software solutions to satisfy the real-time constraints

and to reduce the power consumption.

4 CRM: METHODOLOGY FOR

FEASIBLE RECONFIGURABLE

REAL-TIME EMBEDDED

SYSTEMS

We propose in the current paper a new methodology

CRM that deals with the feasible real-time reconﬁg-

urable MPSoC architectures. We aim to extend the

work in (I. khemaissia and Khalgui, 2014) which is

not interested in the feasibility of the NoC. The differ-

ent steps of this methodology are stated as follows: (i)

Application of reconﬁguration scenarios in different

processors, and (ii) Veriﬁcation of the system’s feasi-

bility, i.e., feasibility of each processor and in NoC.

Before we describe these steps in details, let us

deﬁne the proposed multi-agent architecture.

ICSOFT-EA 2016 - 11th International Conference on Software Engineering and Applications

252

4.1 Multi-agent based Architecture

We deﬁne a multi-agent architecture following the

Master-Slave model: (i) Master Agent Ag

: Respon-

sible of the whole system and the NoC feasibility, (ii)

Slave Agent Ag

i, j

: Deﬁned for each node N

i, j

to in-

form Ag

if the energy increases or if the local real-

time constraints are not satisﬁed. Fig. 3 summarizes

the whole contribution of this current research. It

shows the different states of the system and the pro-

posed agents to resolve any destabilization that can

occur before and after applying any reconﬁguration

scenario.

Figure 3: CRM Methodology.

4.2 System Feasibility

Many solutions are proposed to re-obtain the system

feasibility in all the processors/NoC of RSys after ap-

plying any reconﬁguration scenario that violates real-

time or energy constraints.

4.2.1 Solution 1: Modiﬁcation of Parameters

The utilization must be modiﬁed to ensure the main-

tain of the energy consumption. A technical solution

to be proposed by Ag

allows to change the parame-

ters of all the initial and new tasks. We suggest in the

current work the modiﬁcation of periods as a solution

1.1 or WCETs as a solution 1.2 to guarantee the sat-

isfaction of all the constraints after a such scenario.

According to (I. khemaissia and Khalgui, 2014), the

new periods become:

(r)

i, j,k

(

∑

k=1

(

i, j,k

+ B

i, j,k

)

per

(Pr

i, j

)

(8)

Once the periods are modiﬁed, we calculate the new

processor utilization of periodic tasks U

(r)

perT

as fol-

lows:

(r)

perT

(Pr

i, j

) =

∑

k=1

i, j,k

(r)

i, j,k

(r)

i, j,k

(9)

where n is the number of periodic tasks and r is the

reconﬁguration number. Then, the new power con-

sumption is given by:

(r)

perT

(Pr

i, j

) ∝ (U

(r)

perT

(Pr

i, j

)

) (10)

The new values of the constant period of initial and

new tasks to be executed by Pr

1,1

, that are calculated

by Eq. (8), are equal to 33 Time Units. It is equal

to 49 and 12 for the tasks of Pr

1,2

and Pr

2,1

. Then

the new processor utilizations of Pr

1,1

, Pr

1,2

and Pr

2,1

are equal to 0.54, 0.69 and 0.5, respectively. The peri-

ods modiﬁcation can maintain the utilization of all the

processors of RSys and can stabilize the power con-

sumption. If we modify the WCET of tasks, then the

new C

(r)

are given by:

(r)

i, j,k











⌊

per

(Pr

i, j

)−

∑

k=1

i, j,k

∑

k=1

i, j,k

⌋

1,if

per

(Pr

i, j

)−

∑

k=1

i, j,k

∑

k=1

i, j,k

≤ 0

(11)

After the modiﬁcation of the WCETs, the new pro-

cessor utilization U

(r)

perC

is given by:

(r)

perC

(Pr

i, j

) = (

∑

k=1

(r)

i, j,k

) (12)

The new power consumption is:

(r)

perC

(Pr

i, j

) ∝ (U

(r)

perC

(Pr

i, j

)

) (13)

By using Eq. (11), the new constant WCET of old and

new tasks to be executed by Pr

1,1

and Pr

1,2

is equal

to 2 Time Units. It is equal to T6 Time Units for the

tasks of Pr

2,1

. Hence, the new utilizations of Pr

1,1

1,2

and Pr

2,1

are equal to 0.55, 0.51 and 0.45, re-

spectively. The WCETs modiﬁcation can reduce the

processor utilization of all the processors of RSys and

the power consumption is minimized too. According

to (I. Khemaissia and Khalgui, 2014), if the bus can-

not support the added messages, then we can modify

the parameters of the messages or remove the unim-

portant ones. The new period or the WCTT of each

message is calculated according to (I. Khemaissia and

Khalgui, 2014) as follows:





∑

i=1

NoC

(periodicmessages)





(14)

New Methodology for Feasible Reconﬁgurable Real-Time Network-on-Chip NoC

253











1,0 <

NoC

(periodicmessages)

∑

i=1

≤ 1

⌊

NoC

(periodicmessages)

∑

i=1

⌋,

NoC

(periodicmessages)

∑

i=1

> 1

(15)

where m denotes the number of messages.

After applying Eq. (14), the new utilization of NoC

becomes equal to 0.8. Then the NoC is considered

feasible.

4.2.2 Solution 2: Tasks/Message Removal

As a second solution, Ag

suggests to remove some

OS tasks/messages according to their priorities. If we

need to remove a task with precedence constraints,

then it is necessary to verify if the tasks that depends

on it have a lower priority or not. In this case, the

dependent tasks must be removed from the system.

Otherwise, it is not allowed to remove this task. For

example, if we assume to remove these tasks: A

and

from Pr

1.1

, then its processor utilization becomes

equal to 1. If we remove the tasks with the lowest pri-

ority from all the processors, thus we can reduce the

processor utilization. It is similar for the messages,

i.e., if we remove the messages with the lowest prior-

ity, then the utilization of NoC will be reduced. This

solution can provide a feasible real-time system af-

ter any reconﬁguration scenario but the values of the

processor/NoC utilization depend on the number of

the removed tasks/messages.

4.2.3 Solution 3: Relocation of Tasks according

to the Bin-packing

We use the bin-packing algorithm to relocate the tasks

according to several conditions that will be described

below (Davis, 2006). The system can be reconﬁgured

by Ag

on two levels in order to be temporally fea-

sible with a low-power. Since we can calculate the

processor utilization of each task, two steps must be

done: (a) Step 1: We relocate the tasks by using one

of the proposed algorithms of the bin-packing, and

(b) Step 2: We modify their parameters by follow-

ing Solution 1 if the current utilization of a proces-

sor exceeds 1. Before applying the bin-packing, we

should start by ordering the tasks in an ascending or-

der and the processors in a descending order accord-

ing to their utilization. Two conditions should be sat-

isﬁed when we re-locate a task τ

i, j,k

to Pr

i, j

: (i) Con-

dition 1: the processor Pr

i, j

∈ Inclusion

set

(τ

i, j,k

), and

(ii) Condition 2: U

bef

(Pr

i, j

) ≤ 1. Algorithm 1 de-

scribes the different followed steps in order to relocate

the tasks according to the next ﬁt descending NFD.

Algorithm 1: Relocation of new tasks according to NFD.

Order the processors in an ascending order;

Order the tasks in a descending order;

for (each processor Pr

i, j

) do

for (each task τ

i, j,k

) do

if (Pr

i, j

is active) and (τ

i, j,k

∈

Inclusion

set

(τ

i, j,k

)) then

Calculate the current processor utilization

bef

(Pr

i, j

) after the addition of τ

i, j,k

;

else

if ((U

bef

(Pr

i, j

) ≥ 1) then

Assign τ

i, j,k

to Pr

i, j

that satisﬁes the con-

ditions (conditions 1, 2 and 3);

Re-Calculate U

bef

(Pr

i, j

) after the addi-

tion of τ

i, j,k

to Pr

i, j

;

break;

else

Close the current processor and open the

next one;

Re-Calculate the utilization of the newest

opened processor;

end if

end for

In order to apply the NFD on the running example,

we start by ordering the tasks and the processors in a

descending order and an ascending one, respectively.

We have U

bef

(Pr

1,1

) < U

bef

(Pr

1,2

) < U

bef

(Pr

2,1

). If

we re-order the periodic tasks, we get τ

, τ

. Every time we add a task, we should verify

if the processor can include it. The NFD is applied

as follows: τ

is packed into Pr

1,1

and will be closed.

Since Pr

1,1

/∈ SetInc(τ

), it will be closed and the

current added task is put into Pr

1,2

. The utilization

of Pr

1,2

becomes equal to 1. Then, it will be closed

and Pr

2,1

is open to support τ

. For τ

, it will be

packed into Pr

1,1

that is re-opened since Pr

2,1

is not

mentioned in SetInc(τ

). If we add τ

into Pr

1,1

its utilization becomes equal to 1.1. In this case, Ag

applies the periods modiﬁcation. The same solution

is applied when τ

is added into Pr

1,2

5 EXPERIMENTATION

This section presents an experimentation that applies

low-power reconﬁgurations of MPSoC-based archi-

tectures. We present ﬁrstly the implementation of the

agent-based architecture. After that, theoretical sim-

ulations and analysis are shown to highlight the ad-

vantages of the proposed contribution. We choose to

apply the latter to Stratix III development board.

ICSOFT-EA 2016 - 11th International Conference on Software Engineering and Applications

254

5.1 Implementation of the

Communication Protocol

In this section, we present the main algorithm that

applies the proposed methodology. A protocol is

deﬁned as a system of rules required to make easier

the communication between the different agents

of the system. Before describing the algorithm,

let us present the following used functions. (i)

Send-approval-power(Ag

i, j

,Ag

): If the power

consumption is inferior to 1 after a reconﬁguration

scenario, then Ag

i, j

sends an approval message to

, (ii) Send-alert-power(Ag

i, j

,Ag

): If the power

consumption is superior to 1 after a reconﬁguration

scenario, then Ag

i, j

sends a disapproval message to

, (iii) Evaluate-power-consumption(Ag

): Once

one of the proposed solutions is applied, Ag

com-

putes the difference between the power consumption

before and after the reconﬁguration, (iv) Manage-

removal(Ag

i, j

): Each agent Ag

i, j

must update the

memory after any scenario allowing the removal of

tasks from a processor Pr

i, j

, (v) App-sol1.1(): Peri-

ods modiﬁcation, (vi) App-sol1.2(): WCETs/WCTTs

modiﬁcation, (vii) App-sol2(): Tasks/messages

removal, and (viii) App-sol3(): Re-location by

applying the bin-packing. Algorithm 2 is developed

to control the power consumption by applying new

software solutions. It is with complexity O(n

First of all, it reads the parameters of the initial

tasks. Afterwards, it reads the parameter of the added

messages. Finally, it veriﬁes the feasibility of the

system after the reconﬁguration. If the utilization of

a processor/NoC exceeds 1, then the agent suggests

one of the proposed solutions that are mentioned

previously.

Algorithm 2: Allocations of OS Tasks/Messages to Recon-

ﬁgurable MPSoCs.

for each reconﬁguration scenario do

Compute the utilization U

aft

and the NoC uti-

lization;

if U

aft

≤ 1 or U

NoC

≤ 1 then

Send-approval-power(Ag

i, j

,Ag

);

else

Send-alert-power(Ag

i, j

,Ag

);

Call(App-sol1.1()) or Call(App-sol1.2()) or

Call(App-sol2())or Call(App-sol3());

// Applying one of these solutions

end if

end for

for each processor do

Compute the utilization after reconﬁguration;

Evaluate-power-consumption(Ag

);

end for

0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2

0.5635

0.564

0.5645

0.565

0.5655

0.566

Average U

(ia)

Average P

(i)

Solution 1.1

Figure 4: Power consumption after the periods modiﬁca-

tion.

0.75 0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2

0.35

0.4

0.45

0.5

Processor utilization after the addition of tasks

(i)

WCETs Modification

Figure 5: Power consumption after the WCETs modiﬁca-

tion.

5.2 Simulations

This section presents the obtained results after apply-

ing the proposed solutions. The initial system is as-

sumed to be feasible with low-power. The processor

utilization of each processor Pr

1,1

, Pr

1,2

, and Pr

2,1

equal to 0.696532, 0.751534 and 0.803858, respec-

tively. Fig. 4 depicts the power consumption after the

modiﬁcation of the periods and the WCETs. We can

deduce that the periods modiﬁcation can stabilize the

power consumption. But, the WCETs modiﬁcation

can reduce the power consumption since the curves

show important variations. We can conclude that this

theoretical simulation result by Solution 1.2 is more

advantageous than Solution 1.1. Fig. 6 visualizes the

simulation result after applying the bin-packing algo-

rithm. The different values of the power consumption

are in the closed interval [0.5635..0.5655] . Then, we

can neglect the variations. This solution is considered

as effective as well.

6 CONCLUSION

In this paper, a new approach called CRM is devel-

oped for low-power reconﬁgurable MPSoC-based ar-

chitectures. Initially, the system is feasible with low-

New Methodology for Feasible Reconﬁgurable Real-Time Network-on-Chip NoC

255

0.8 0.85 0.9 0.95 1 1.05 1.1 1.15 1.2

0.563

0.5635

0.564

0.5645

0.565

0.5655

0.566

Average U

(ia)

Average P

(i)

BFD

FFD

NFD

RFD

WFD

Figure 6: Power consumption after applying the bin-

packing.

power. However, after many reconﬁguration scenar-

ios, the power consumption becomes bigger and some

real-time requirements may not be satisﬁed. A multi-

agent architecture based on the master-slave model

is proposed, where software/hardware technical solu-

tions are applied in order to obtain a feasible real-time

system guaranteeing the minimization or the maintain

of the power consumption. This new methodology

is applied to conﬁdential projects at Cynapsys. To

our best knowledge, no studies dealing with reconﬁg-

urable real-time MPSoC under low-power constraints

were suggested before. As a future work, we will

be interested in aperiodic/sporadic tasks. Also, we

will be interested in the reconﬁgurable routing of pe-

riodic/sporadic messages under low-power and low-

memory constraints.

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