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Authors: Alexander Biedermann ; Thorsten Piper ; Lars Patzina ; Sven Patzina ; Sorin A. Huss ; Andy Schürr and Neeraj Suri

Affiliation: CASED - Center for Advanced Security Research Darmstadt, Germany

Keyword(s): System monitoring, Embedded HW/SW design, FPGA monitoring.

Related Ontology Subjects/Areas/Topics: Detection and Estimation ; Digital Signal Processing ; Embedded Communications Systems ; Instrumentation and Measurement ; Networking and Connectivity ; Sensors and Sensor Networks ; Telecommunications

Abstract: Today, state of the art technology allows a very dense integration of embedded HW/SW designs. As a consequence, more errors are introduced in these circuits that have to be observed during run-time. Adding monitors to a design enables the recognition of and the reaction to these threats, but, usually, monitors have to be developed for every individual FPGA design. Our approach provides generic IP cores that permit the monitoring of arbitrary hardware modules. Furthermore, by providing a central monitoring module, statements about the behaviour of the entire system can be made.

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Paper citation in several formats:
Biedermann, A.; Piper, T.; Patzina, L.; Patzina, S.; A. Huss, S.; Schürr, A. and Suri, N. (2011). ENHANCING FPGA ROBUSTNESS VIA GENERIC MONITORING IP CORES. In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - PECCS; ISBN 978-989-8425-48-5; ISSN 2184-2817, SciTePress, pages 379-386. DOI: 10.5220/0003353503790386

@conference{peccs11,
author={Alexander Biedermann. and Thorsten Piper. and Lars Patzina. and Sven Patzina. and Sorin {A. Huss}. and Andy Schürr. and Neeraj Suri.},
title={ENHANCING FPGA ROBUSTNESS VIA GENERIC MONITORING IP CORES},
booktitle={Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - PECCS},
year={2011},
pages={379-386},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003353503790386},
isbn={978-989-8425-48-5},
issn={2184-2817},
}

TY - CONF

JO - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - PECCS
TI - ENHANCING FPGA ROBUSTNESS VIA GENERIC MONITORING IP CORES
SN - 978-989-8425-48-5
IS - 2184-2817
AU - Biedermann, A.
AU - Piper, T.
AU - Patzina, L.
AU - Patzina, S.
AU - A. Huss, S.
AU - Schürr, A.
AU - Suri, N.
PY - 2011
SP - 379
EP - 386
DO - 10.5220/0003353503790386
PB - SciTePress

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