Authors:
Andrea Enrici
1
;
Julien Lallet
1
;
Imran Latif
1
;
Ludovic Apvrille
2
;
Renaud Pacalet
2
and
Adrien Canuel
2
Affiliations:
1
Nokia Bell Labs, France
;
2
LTCI, Télécom ParisTech and Université Paris-Saclay, France
Keyword(s):
Domain-specific Modeling, Model Transformation, Model-driven Architecture.
Related
Ontology
Subjects/Areas/Topics:
Domain-Specific Modeling and Domain-Specific Languages
;
Languages, Tools and Architectures
;
Model Transformation
;
Model-Driven Architecture
;
Model-Driven Software Development
;
Models
;
Paradigm Trends
;
Software Engineering
Abstract:
To meet the computational and flexibility requirements of future 5G networks, the signal-processing functions of baseband stations and user equipments will be accelerated onto programmable, configurable and hard-wired components (e.g., CPUs, FPGAs, hardware accelerators). Such mixed architectures urge the need to automatically generate efficient implementations from high-level models. Existing model-based approaches can generate executable implementations of Systems-on-Chip (SoCs) by translating models into multiple SoC-programming languages (e.g., C/C++, OpenCL, Verilog/VHDL). However, these translations do not typically consider the optimization of non-functional properties (e.g., memory footprint, scheduling). This paper proposes a novel approach where system-level models are optimized and compiled into multiple implementations for different SoC architectures. We show the effectiveness of our approach with the compilation of UML/SysML models of a 5G decoder. Our solution generates
both a software implementation for a Digital Signal Processor platform and a hardware-software implementation for a platform based on hardware Intellectual Property (IP) blocks. Overall, we achieve a memory footprint reduction of 80.07% in the first case and 88.93% in the second case.
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