Authors:
Peter T. Breuer
1
;
Jonathan P. Bowen
2
;
Esther Palomar
3
and
Zhiming Liu
4
Affiliations:
1
Hecusys LLC, United States
;
2
London South Bank University, United Kingdom
;
3
Birmingham City University, United Kingdom
;
4
Southwest University, China
Keyword(s):
Computer Security, Encrypted Computing, Computer Architecture, Applied Cryptography.
Related
Ontology
Subjects/Areas/Topics:
Applied Cryptography
;
Critical Infrastructure Protection
;
Cryptographic Techniques and Key Management
;
Data and Application Security and Privacy
;
Data Engineering
;
Data Integrity
;
Data Protection
;
Databases and Data Security
;
Information and Systems Security
;
Security and Privacy in the Cloud
Abstract:
This paper explores a new approach to encrypted microprocessing, potentiating new trade-offs in security
versus performance engineering. The coprocessor prototype described runs standard machine code (32-bit
OpenRISC v1.1) with encrypted data in registers, on buses, and in memory. The architecture is ‘superscalar’,
executing multiple instructions simultaneously, and is sophisticated enough that it achieves speeds approaching
that of contemporary off-the-shelf processor cores.
The aim of the design is to protect user data against the operator or owner of the processor, and so-called
‘Iago’ attacks in general, for those paradigms that require trust in data-heavy computations in remote locations
and/or overseen by untrusted operators. A single idea underlies the architecture, its performance and security
properties: it is that a modified arithmetic is enough to cause all program execution to be encrypted. The
privileged operator, running unencrypted with the standard arithmetic, can see
and try their luck at modifying
encrypted data, but has no special access to the information in it, as proven here. We test the issues, reporting
performance in particular for 64-bit Rijndael and 72-bit Paillier encryptions, the latter running keylessly.
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