Authors:
Choucha Chams Eddine
1
;
Mohamed Oussama Ben Salem
2
;
Mohamed Oussama Khalgui
3
;
Laid Kahloul
4
and
Naima Souad Ougouti
5
Affiliations:
1
LISI Laboratory, National Institute of Applied Sciences and Technology (INSAT), University of Carthage, Tunis 1080, Tunisia
;
2
Team Project IMAGES-ESPACE-Dev, UMR 228 EspaceDev IRD UA UM UG UR, University of Perpignan Via Domitia, Perpignan 66860, France
;
3
LISI Laboratory, National Institute of Applied Sciences and Technology (INSAT), University of Carthage, Tunis 1080, Tunisia, School of Electrical and Information Engineering, Jinan University, Zhuhai Campus, Zhuhai 519070, China
;
4
LINFI Laboratory, Computer Science Department, Biskra University, Biskra, Algeria
;
5
LSSD Laboratory, Computer Science Department, University of Science and Technology of Oran Mohamd Boudiaf, Algeria
Keyword(s):
Formal Verification, Discrete-event System, Reconfiguration, Petri Net, Ontology.
Abstract:
Reconfigurable discrete event control systems (RDECSs) are complex and critical systems, motivating the use of formal verification. This verification consists of two major steps: state space generation and state space analysis. The application of the mentioned steps is usually expensive in terms of computation time and memory. This paper deals with state space generation (accessibility graph generation) during verification of RDECSs modeled with specified reconfigurable timed net condition/event systems (R-TNCESs). We aim to improve model checking used for formal verification of RDECSs by proposing a new aproach of state space generation that considers similarities. In this approach, we introduce the modularity concept for verifying systems by constructing incrementally their accessibility graphs. Furthermore, we set up an ontology-based history to deal with similarities between two or several systems by reusing state spaces of similar components that are computed during previous ver
ification. A distributed cloud-based architecture is proposed to perform the parallel computation for control verification time and memory occupation. The paper’s contribution is applied to a benchmark production system. The evaluation of the proposed approach is performed by measuring the temporal complexity of several large scale system verification. The results show the relevance of this approach.
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