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Authors: Bakiri Mohammed 1 ; Jean-François Couchot 2 and Christophe Guyeux 2

Affiliations: 1 University of Franche-Comté, Centre de Développement des Technologies Avancées and, France ; 2 University of Franche-Comté, France

ISBN: 978-989-758-196-0

Keyword(s): Random Number Generators, System on Chip, FPGA, High Level Synthesis, RTL, Chaotic Iterations, Statistical Tests, Security.

Related Ontology Subjects/Areas/Topics: Applied Cryptography ; Cryptographic Techniques and Key Management ; Data Engineering ; Databases and Data Security ; Information and Systems Security ; Network Security ; Security in Information Systems ; Security Information Systems Architecture and Design and Security Patterns ; Software Security ; Ubiquitous Computing Security

Abstract: Pseudorandom number generation (PRNG) is a key element in hardware security platforms like fieldprogrammable gate array FPGA circuits. In this article, 18 PRNGs belonging in 4 families (xorshift, LFSR, TGFSR, and LCG) are physically implemented in a FPGA and compared in terms of area, throughput, and statistical tests. Two flows of conception are used for Register Transfer Level (RTL) and High-level Synthesis (HLS). Additionally, the relations between linear complexity, seeds, and arithmetic operations on the one hand, and the resources deployed in FPGA on the other hand, are deeply investigated. In order to do that, a SoC based on Zynq EPP with ARM Cortex-A9 MPSoC is developed to accelerate the implementation and the tests of various PRNGs on FPGA hardware. A case study is finally proposed using chaotic iterations as a post processing for FPGA. The latter has improved the statistical profile of a combination of PRNGs that, without it, failed in the so-called TestU01 statistical batte ry of tests. (More)

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Paper citation in several formats:
Mohammed, B.; Couchot, J. and Guyeux, C. (2016). FPGA Implementation of F2-Linear Pseudorandom Number Generators based on Zynq MPSoC: A Chaotic Iterations Post Processing Case Study.In Proceedings of the 13th International Joint Conference on e-Business and Telecommunications - Volume 4: SECRYPT, (ICETE 2016) ISBN 978-989-758-196-0, pages 302-309. DOI: 10.5220/0005967903020309

@conference{secrypt16,
author={Bakiri Mohammed. and Jean{-}Fran\c{C}ois Couchot. and Christophe Guyeux.},
title={FPGA Implementation of F2-Linear Pseudorandom Number Generators based on Zynq MPSoC: A Chaotic Iterations Post Processing Case Study},
booktitle={Proceedings of the 13th International Joint Conference on e-Business and Telecommunications - Volume 4: SECRYPT, (ICETE 2016)},
year={2016},
pages={302-309},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0005967903020309},
isbn={978-989-758-196-0},
}

TY - CONF

JO - Proceedings of the 13th International Joint Conference on e-Business and Telecommunications - Volume 4: SECRYPT, (ICETE 2016)
TI - FPGA Implementation of F2-Linear Pseudorandom Number Generators based on Zynq MPSoC: A Chaotic Iterations Post Processing Case Study
SN - 978-989-758-196-0
AU - Mohammed, B.
AU - Couchot, J.
AU - Guyeux, C.
PY - 2016
SP - 302
EP - 309
DO - 10.5220/0005967903020309

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