Authors:
Maamar Hamri
1
and
Nesrine Driouche
2
Affiliations:
1
Aix Marseille Université, CNRS, ENSAM and Université de Toulon, France
;
2
Independant Software Researcher, France
Keyword(s):
Logic Gates, DEVS, Modeling and Simulation, Performances.
Related
Ontology
Subjects/Areas/Topics:
Discrete-Event Simulation
;
Formal Methods
;
Performance Analysis
;
Simulation and Modeling
;
Simulation Tools and Platforms
Abstract:
Discrete event simulation becomes popular more and more and was applied successfully in many fields:
medicine, robotics, etc. One of this field is digital circuits for which boolean logics is the basis of computation
by designing logic gates. However such a paradigm does not consider the time basis. Consequently, the
boolean logic paradigm can not design and simulate delays of circuits and stamped explicitly computations.
In this paper, we propose to combine the boolean logic paradigm and Discrete EVent system Specification
(DEVS) formalism for modeling and simulation logic gates. Using this approach, we are able to design complex
network of logic gates by reusing and coupling basic ones and to analyze behavior through time.