Authors:
Prateek Saxena
1
;
Vinay B. Y. Kumar
1
;
Dilawar Singh
1
;
H Narayanan
2
and
Sachin B. Patkar
1
Affiliations:
1
Indian Institute of Technology Bombay, India
;
2
Indian Institute of Technology and Bombay, India
Keyword(s):
Galois Field Matrix Computations and Linear Equation Solvers, GF(2), Block Gaussian Elimination with Pivoting over GF(2), Hardware/Software Co-design, Custom Processor Extensions.
Related
Ontology
Subjects/Areas/Topics:
Embedded Communications Systems
;
Telecommunications
;
VLSI Design and Implementation
Abstract:
Solving a System of Linear Equations over Finite Fields finds one of the
most important practical applications, for instance, in problems arising in
cryptanalysis and network coding among others. However, other than
software-only approaches to acceleration, the amount of focus particularly
towards hardware or hardware/software based solutions is small, in comparison to that towards
general linear equation solvers.
We present scalable architectures for Gaussian elimination with pivoting over
GF(2) and higher fields, both as custom extensions to commodity processors or as dedicated hardware for
larger problems. In particular, we present:
1) Designs of components---Matrix Multiplication and `Basis search and Inversion'---for Gaussian elimination over GF(2), prototyped as custom instruction extensions to Nios-II on DE2-70(DE2, 2008), which even with a 50MHz clock perform at $\approx$30~GOPS (billion GF(2) operations); and
also report results for GF($2^8$) or higher order matrix multipl
ication with about 20~GOPS performance at 200MBps.
2) A scalable extension of a previous design [Bogdanov et. al, 2006] for multiple FPGAs and with $\approx$2.5 TrillionOPS performance at ~5GBps bandwidth on a Virtex-5 FPGA
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