Authors:
Jean-Marie Gauthier
;
Fabrice Bouquet
;
Ahmed Hammad
and
Fabien Peureux
Affiliation:
FEMTO-ST Institute, France
Keyword(s):
SysML, VHDL-AMS, Verification, Validation, Unit Testing, Meta-model Transformation, Code Generation.
Related
Ontology
Subjects/Areas/Topics:
Agile Model-Driven Development
;
Applications and Software Development
;
Frameworks for Model-Driven Development
;
Languages, Tools and Architectures
;
MetaModeling
;
Methodologies, Processes and Platforms
;
Model Execution and Simulation
;
Model Transformation
;
Model Transformations and Generative Approaches
;
Model-Based Testing and Validation
;
Model-Driven Architecture
;
Model-Driven Software Development
;
Model-Driven Systems Engineering
;
Models
;
Paradigm Trends
;
Software Engineering
Abstract:
This paper proposes an approach to verify SysML models consistency and to validate the transformation of
SysML models to VHDL-AMS code. This approach is based on two main solutions: the use of model-to-model
transformation to verify SysML models consistency and writing unit tests to validate model transformations.
The translation of SysML models into VHDL-AMS simulable code uses MMT (Model to Model Transformation)
ATL Atlas Transformation Language and M2T (Model To Text) Acceleo tooling. The test validation of
the model transformations is performed using EUNIT framework.