Authors:
Hui Xu
;
Feng Zhao
and
Ran Ju
Affiliation:
Shanghai Jiao Tong University, China
Keyword(s):
Hardware, Object detection, AdaBoost algorithm.
Related
Ontology
Subjects/Areas/Topics:
Computer Vision, Visualization and Computer Graphics
;
Image Formation and Preprocessing
;
Implementation of Image and Video Processing Systems
Abstract:
This paper implements a hardware architecture for object detection based on AdaBoost learning algorithm and Haar-like features. To increase detection speed and reduce hardware consumption, an integral image calculation array with pipelined feature data flow are introduced. Input images are scanned by sub-windows and detected by cascade classifiers. Moreover, special design is made to enhance the parallelism of the architecture. In comparison with the original design, detection speed is improved by three, with only 5% increase in hardware consumption. The final hardware detection system, implemented on Xilinx V2pro FPGA platform, reaches the detection speed of 80 f ps and consumes 91% resources of the platform.