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Authors: N. V. Kuznetsov 1 ; G. A. Leonov 1 ; S. M. Seledzhi 1 and P. Neittaanmäki 2

Affiliations: 1 Saint-Petersburg State University, Russian Federation ; 2 University of Jyväskylä, Finland

Keyword(s): Delay line, Phase locked loop, Nonlinear analysis, Clocked circuit.

Related Ontology Subjects/Areas/Topics: Informatics in Control, Automation and Robotics ; Nonlinear Signals and Systems ; Signal Processing, Sensors, Systems Modeling and Control ; Time Series and System Modeling

Abstract: In this work classical and modern control theory methods are applied for rigorous mathematical analysis and design of different computer architecture circuits such as clock generators, synchronization systems and others. The present work is devoted to the questions of analysis and synthesis of feedback systems, in which there are controllable delay lines. In the work it is mathematically strictly shown that RC-chain can be used as a controllable delay line for different problems of circuit engineering if the chain is sequentially connected with hysteretic relay. This relay is either artificially introduced or shows itself as non-ideality of logic elements. The possibility of phase-locked loop application for time delay control is considered.

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Paper citation in several formats:
V. Kuznetsov, N.; A. Leonov, G.; M. Seledzhi, S. and Neittaanmäki, P. (2009). ANALYSIS AND DESIGN OF COMPUTER ARCHITECTURE CIRCUITS WITH CONTROLLABLE DELAY LINE. In Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 2: ICINCO; ISBN 978-989-674-001-6; ISSN 2184-2809, SciTePress, pages 221-224. DOI: 10.5220/0002205002210224

@conference{icinco09,
author={N. {V. Kuznetsov}. and G. {A. Leonov}. and S. {M. Seledzhi}. and P. Neittaanmäki.},
title={ANALYSIS AND DESIGN OF COMPUTER ARCHITECTURE CIRCUITS WITH CONTROLLABLE DELAY LINE},
booktitle={Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 2: ICINCO},
year={2009},
pages={221-224},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002205002210224},
isbn={978-989-674-001-6},
issn={2184-2809},
}

TY - CONF

JO - Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 2: ICINCO
TI - ANALYSIS AND DESIGN OF COMPUTER ARCHITECTURE CIRCUITS WITH CONTROLLABLE DELAY LINE
SN - 978-989-674-001-6
IS - 2184-2809
AU - V. Kuznetsov, N.
AU - A. Leonov, G.
AU - M. Seledzhi, S.
AU - Neittaanmäki, P.
PY - 2009
SP - 221
EP - 224
DO - 10.5220/0002205002210224
PB - SciTePress

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