Authors:
Eloy Parra-Barrero
1
;
Jorge Fernández-Berni
2
;
Fernanda D. V. R. Oliveira
3
;
Ricardo Carmona-Galán
2
and
Ángel Rodríguez-Vázquez
2
Affiliations:
1
Universidad de Sevilla, Spain
;
2
Instituto de Microelectrónica de Sevilla (IMSE-CNM) and CSIC-Universidad de Sevilla, Spain
;
3
Universidade Federal do Rio de Janeiro, Brazil
Keyword(s):
Embedded Systems, Vision Pipeline, Early Vision, Smart Image Sensors, Vision Chips, Focal-plane Processing, Object Detection, Viola-Jones Algorithm, Performance, Processing Acceleration.
Related
Ontology
Subjects/Areas/Topics:
Applications and Services
;
Camera Networks and Vision
;
Computer Vision, Visualization and Computer Graphics
;
Features Extraction
;
Image and Video Analysis
;
Image Formation and Preprocessing
;
Image Formation, Acquisition Devices and Sensors
;
Image Generation Pipeline: Algorithms and Techniques
;
Pervasive Smart Cameras
Abstract:
Smart CMOS image sensors can leverage the inherent data-level parallelism and regular computational flow of early vision by incorporating elementary processors at pixel level. However, it comes at the cost of extra area having a strong impact on the sensor sensitivity, resolution and image quality. In this scenario, the fundamental challenge is to devise new strategies capable of boosting the performance of the targeted vision pipeline while minimally affecting the sensing function itself. Such strategies must also feature enough flexibility to accommodate particular application requirements. From these high-level specifications, we propose a focal-plane processing architecture tailored to speed up object detection via the Viola-Jones algorithm. This architecture is supported by only two extra transistors per pixel and simple peripheral digital circuitry that jointly make up a massively parallel reconfigurable processing lattice. A performance evaluation of the proposed scheme in ter
ms of accuracy and acceleration for face detection is reported.
(More)