Authors:
Salah Harb
;
M. Ahmad
and
M. Swamy
Affiliation:
Electrical and Computer Engineering Department, Concordia University, 1440 De maisonnueve, Montreal, Canada
Keyword(s):
Information Hiding, Steganography, Communication Systems, FPGA, Pipelined Architecture, Efficiency.
Abstract:
In this paper, we introduce a high-speed and area-efficient hardware design for a novel modulus-based image steganographic scheme, specifically targeting constrained-area steganographic embedded systems. The proposed modulus-based image steganography scheme enhances both image quality and embedding rate while ensuring resilience against PVD histogram analysis, salt-and-pepper noise, and RS analysis attack. The hardware architecture incorporates pipelined registers placed to guarantee balanced-execution paths among computing components. A memory-less finite state machine model is developed to efficiently control the instructions for the steganographic operations. Employing a hardware-software co-design approach, the proposed hardware design is realized as an IP core on the AMD Xilinx Zynq-7000 APSoC platform. It processes concealing operations in just 13 clock cycles, utilizes 148 slices, and operates at 290 MHz. This results in a remarkable throughput of 2.32 Gbps. The hardware desig
n demonstrates significant improvements in speed, resource utilization, and throughput compared to recent steganographic hardware implementations, making it ideal for resource-constrained, real-time applications ranging from secure embedded communication to advanced IoT data protection.
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