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Authors: Sumedh Attarde 1 ; Siddharth Joshi 2 ; Yash Deshpande 1 ; Sunil Puranik 3 and Sachin Patkar 1

Affiliations: 1 Indian Institute of Technology Bombay, India ; 2 EE and IIT Bombay, India ; 3 Computational Research Laboratories, India

Keyword(s): Sparse matrix vector multiplication, FPGA, Embedded scientific computing, DRAM.

Related Ontology Subjects/Areas/Topics: Embedded Communications Systems ; Telecommunications ; VLSI Design and Implementation

Abstract: In this paper, we present the design of an embedded system performing double precision sparse matrix vector multiplication (SpMxV), a key scientific computation kernel in iterative solvers, for very large matrices (millions of rows). The embedded system is implemented using the Xilinx MicroBlaze platform on the XUPV5-LX110T FPGA development board. Due to their size, matrices generally encountered in scientific computation need to be stored on off-chip DRAMs. A novel processing paradigm involving blocking of the matrix, and a novel data access mechanism which pre-fetches required data in bursts from off-chip DRAMS to hide large DRAM random access latencies are proposed and implemented. The processing element has been implemented as a prototype accelerator peripheral in an embedded system for the iterative Gauss-Jacobi algorithm.

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Paper citation in several formats:
Attarde, S.; Joshi, S.; Deshpande, Y.; Puranik, S. and Patkar, S. (2011). DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA. In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - PECCS; ISBN 978-989-8425-48-5; ISSN 2184-2817, SciTePress, pages 476-484. DOI: 10.5220/0003400804760484

@conference{peccs11,
author={Sumedh Attarde. and Siddharth Joshi. and Yash Deshpande. and Sunil Puranik. and Sachin Patkar.},
title={DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA},
booktitle={Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - PECCS},
year={2011},
pages={476-484},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003400804760484},
isbn={978-989-8425-48-5},
issn={2184-2817},
}

TY - CONF

JO - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - PECCS
TI - DOUBLE PRECISION SPARSE MATRIX VECTOR MULTIPLICATION ACCELERATOR ON FPGA
SN - 978-989-8425-48-5
IS - 2184-2817
AU - Attarde, S.
AU - Joshi, S.
AU - Deshpande, Y.
AU - Puranik, S.
AU - Patkar, S.
PY - 2011
SP - 476
EP - 484
DO - 10.5220/0003400804760484
PB - SciTePress

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