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Authors: Marek Bohrn and Lukas Fujcik

Affiliation: Brno University of Technology, Czech Republic

Keyword(s): Artificial neural networks, Computation acceleration, FPGA, VHDL, Spartan-3.

Related Ontology Subjects/Areas/Topics: Artificial Intelligence ; Artificial Intelligence and Decision Support Systems ; Computational Intelligence ; Enterprise Information Systems ; Image Processing ; Informatics in Control, Automation and Robotics ; Intelligent Control Systems and Optimization ; Neural Networks Based Control Systems ; Optimization Algorithms ; Optimization Problems in Signal Processing ; Robotics and Automation ; Signal Processing, Sensors, Systems Modeling and Control ; Soft Computing

Abstract: This article describes a design and features of a multi-core unit for performing computing operations required for artificial neural network functioning. Its purpose is to speed up computing operations of the neural network. The number of computing cores can be altered as needed to achieve the required performance. VHDL language has been used to build this module. It has been optimized for the Spartan-3 family FPGA chips from Xilinx. These chips are favorable because of their low price and a high number of on-chip multipliers and block memory units. Spartan-3 chips facilitate parallel computing operations within neural networks to a very high level and thus help to achieve high computing power.

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Paper citation in several formats:
Bohrn, M. and Fujcik, L. (2009). MULTI-CORE COMPUTING UNIT FOR ARTIFICIAL NEURAL NETWORKS IN FPGA CHIP. In Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO; ISBN 978-989-8111-99-9; ISSN 2184-2809, SciTePress, pages 149-152. DOI: 10.5220/0002172101490152

@conference{icinco09,
author={Marek Bohrn. and Lukas Fujcik.},
title={MULTI-CORE COMPUTING UNIT FOR ARTIFICIAL NEURAL NETWORKS IN FPGA CHIP},
booktitle={Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO},
year={2009},
pages={149-152},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002172101490152},
isbn={978-989-8111-99-9},
issn={2184-2809},
}

TY - CONF

JO - Proceedings of the 6th International Conference on Informatics in Control, Automation and Robotics - Volume 3: ICINCO
TI - MULTI-CORE COMPUTING UNIT FOR ARTIFICIAL NEURAL NETWORKS IN FPGA CHIP
SN - 978-989-8111-99-9
IS - 2184-2809
AU - Bohrn, M.
AU - Fujcik, L.
PY - 2009
SP - 149
EP - 152
DO - 10.5220/0002172101490152
PB - SciTePress

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