Authors:
Guangling Dong
1
;
Chi He
2
;
Zhenguo Dai
3
;
Yanchang Huang
3
and
Xiaochu Hang
3
Affiliations:
1
Harbin Institute of Technology, China
;
2
CUST, China
;
3
Baicheng Ordnance Test Center of China, China
Keyword(s):
Missile Hit Accuracy, Integrated Test Design, Bayesian Sample Size Determination, Power Prior, Design Prior.
Related
Ontology
Subjects/Areas/Topics:
Application Domains
;
Artificial Intelligence
;
Formal Methods
;
Informatics in Control, Automation and Robotics
;
Intelligent Control Systems and Optimization
;
Military and Defense
;
Optimization Issues
;
Performance Analysis
;
Planning and Scheduling
;
Simulation and Modeling
;
Simulation Tools and Platforms
;
Symbolic Systems
Abstract:
Sample size determination (SSD) for integrated test of missile hit accuracy is addressed in this paper.
Bayesian approach to SSD gives test designer the possibility of taking into account of prior information and
uncertainty on unknown parameters of interest. This fact offers the advantage of removing or mitigating
typical drawbacks of classical methods, which might lead to serious miscalculation of the sample size.
However, standard power prior based Bayesian SSD method cannot cope with integrated SSD for both
simulation test and field test, as large numbers of simulation samples would cause contradiction between
design prior and average posterior variance criterion (APVC). In allusion to this problem, we propose a test
design effect equivalent method for equivalent sample size (ESS) calculation, which combined simulation
credibility, sample size, and power prior exponent to get a rational design prior for subsequent field test.
Average posterior variance (APV) of interested paramet
ers is deduced by simulation credibility, sample
sizes of two kinds of test, and prior distribution parameters. Thus, we get optimal design equations of
integrated test scheme under both test cost constraints and required posterior precision constraint, whose
effectiveness are illustrated with two examples.
(More)