Authors:
Kawtar Benghazi Akhlaki
1
;
Manuel I. Capel Tuñón
1
;
Juan A. Holgado Terriza
1
and
Luis E. Mendoza Morales
2
Affiliations:
1
ETSI Informáticos, Universidad de Granada, Spain
;
2
Universidad Simón Bolívar, Venezuela
Keyword(s):
Timed Sequence Diagram, State Diagram, Formal semantics, CSP+T, Timed Traces. Timing Constraints.
Related
Ontology
Subjects/Areas/Topics:
Enterprise Information Systems
;
Information Systems Analysis and Specification
;
Methodologies, Processes and Platforms
;
Model-Driven Software Development
;
Modeling Formalisms, Languages and Notations
;
Software Engineering
;
Systems Engineering
Abstract:
Having an objective of achieving a formal characterisation of Sequence Diagrams (UML-SD) as a means for Embedded Real-Time software systems ( ERTS ) development and validation, this paper introduces a CSP+T- based timed trace semantics for most concepts of SD. A trace is sequence of events, which gives the necessary expressiveness to capture the standard interpretation of UML SD. Timed SD (TSD) depict work flow, message passing and gives a general view of how system’s components cooperate over time to achieve a result. Such sequence, often called an scenario, also represents a part of the system behaviour and a possible execution of a state machine. State machines and SD are used as complementary models for describing system behaviour.