Authors:
Carlos Alberto de Albuquerque Silva
;
Anthony Andrey Ramalho Diniz
;
Adrião Duarte Dória Neto
and
Jose Alberto Nicolau de Oliveira
Affiliation:
Universidade Federal do Rio Grande do Norte – UFRN, Brazil
Keyword(s):
FPGA, Partial Reconfiguration, Artificial Neural Networks.
Related
Ontology
Subjects/Areas/Topics:
Embedded Communications Systems
;
Software Architectures
;
Telecommunications
Abstract:
This paper is focused on partial reconfiguration of Field Programmable Gate Arrays (FPGAs) Virtex$\circledR$-6, produced by Xilinx$\circledR$, and its application implementing Artificial Neural Networks (ANNs) of Multilayer Perceptron (MLP) type. This FPGA can be partially reprogramed without suspending operation in other parts that do not need reconfiguration. It can be performed by specifying the Modular Project’s flow, where the modules that compose the project can be synthesized separately, and, after that, reunited in another module of highest hierarchical level. Alternatively, it is possible developing reconfigurable modules inserted in partial bitstreams and, later, downloading partial bitstreams successively in hardware. Therefore, it is possible configuring topologies of different MLP networks by using partial bitstreams in reconfigurable areas. It is expected that, in this kind of hardware, applications with MLP ANNs be easily embedded, and also allow easily configuration o
f many kinds of MLP networks in field.
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