Authors:
Daniela Genius
1
;
Letitia W. Li
2
;
Ludovic Apvrille
3
and
Tullio Tanzi
4
Affiliations:
1
Sorbonne Universites, UPMC Paris 06, LIP6 and CNRS UMR 7606, France
;
2
LTCI, Télécom ParisTech, Université Paris-Saclay and Institut VEDECOM, France
;
3
LTCI, Télécom ParisTech and Université Paris-Saclay, France
;
4
Télécom ParisTech, Université Paris-Saclay, LTCI, Télécom ParisTech and Université Paris-Saclay, France
Keyword(s):
Embedded Systems, System-level Design, Simulation, Virtual Prototyping, Latency.
Related
Ontology
Subjects/Areas/Topics:
Applications and Software Development
;
Frameworks for Model-Driven Development
;
Methodologies, Processes and Platforms
;
Model Execution and Simulation
;
Model-Driven Software Development
;
Models
;
Paradigm Trends
;
Software Engineering
;
Systems Engineering
Abstract:
Designing embedded systems includes two main phases: (i) HW/SW Partitioning performed from high-level
functional and architecture models, and (ii) Software Design performed with significantly more detailed models.
Partitioning decisions are made according to performance assumptions that should be validated on the
more refined software models. In this paper, we focus on one such metric: latencies between operations. We
show how they can be modeled at different abstraction levels (partitioning, SW design) and how they can help
determine accuracy of the computational complexity estimates made during HW/SW Partitioning.