EFFICIENT DESIGN OF BIT-LEVEL ACCELERATOR ARCHITECTURES FOR THE DEDR-RASF REMOTE SENSING ALGORITHM USING SUPER-SYSTOLIC ARRAYS Topics: Real-Time Systems; Remote Sensing and Signal Processing; VLSI Design and Implementation In Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems PECCS - Volume 1, 327-333, 2012 , Rome, Italy