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Authors: A. Castillo Atoche 1 ; J. Estrada Lopez 1 ; R. Quijano Cetina 1 and L. Rizo Dominguez 2

Affiliations: 1 Autonomous University of Yucatan, Mexico ; 2 University of Caribe, Mexico

Keyword(s): Remote sensing, Parallel computing, Super-systolic arrays, FPGA design.

Related Ontology Subjects/Areas/Topics: Digital Signal Processing ; Embedded Communications Systems ; Real-Time Systems ; Remote Sensing and Signal Processing ; Telecommunications ; VLSI Design and Implementation

Abstract: In this paper, we propose bit-level hardware accelerator architectures for real time implementation of large-scale remote sensing (RS) imaging. The computational complex RS operations of the DEDR-RASF algorithm are implemented in efficient bit-level high-throughput accelerators units. Super-Systolic Arrays (SSAs) and High Performance Embedded Computing (HPEC) techniques were used in aggregation with a HW/SW co-design scheme, achieving the required real-time data processing for newer RS applications. The bit-level SSA accelerators were implemented in a Virtex 5 XC5VFX130T Field Programable Gate Array (FPGA) technology. Performance results revels the significant improvement in both area and time metrics over previous works.

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Paper citation in several formats:
Castillo Atoche, A.; Estrada Lopez, J.; Quijano Cetina, R. and Rizo Dominguez, L. (2012). EFFICIENT DESIGN OF BIT-LEVEL ACCELERATOR ARCHITECTURES FOR THE DEDR-RASF REMOTE SENSING ALGORITHM USING SUPER-SYSTOLIC ARRAYS. In Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - PECCS; ISBN 978-989-8565-00-6; ISSN 2184-2817, SciTePress, pages 327-333. DOI: 10.5220/0003835203270333

@conference{peccs12,
author={A. {Castillo Atoche}. and J. {Estrada Lopez}. and R. {Quijano Cetina}. and L. {Rizo Dominguez}.},
title={EFFICIENT DESIGN OF BIT-LEVEL ACCELERATOR ARCHITECTURES FOR THE DEDR-RASF REMOTE SENSING ALGORITHM USING SUPER-SYSTOLIC ARRAYS},
booktitle={Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - PECCS},
year={2012},
pages={327-333},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003835203270333},
isbn={978-989-8565-00-6},
issn={2184-2817},
}

TY - CONF

JO - Proceedings of the 2nd International Conference on Pervasive Embedded Computing and Communication Systems - PECCS
TI - EFFICIENT DESIGN OF BIT-LEVEL ACCELERATOR ARCHITECTURES FOR THE DEDR-RASF REMOTE SENSING ALGORITHM USING SUPER-SYSTOLIC ARRAYS
SN - 978-989-8565-00-6
IS - 2184-2817
AU - Castillo Atoche, A.
AU - Estrada Lopez, J.
AU - Quijano Cetina, R.
AU - Rizo Dominguez, L.
PY - 2012
SP - 327
EP - 333
DO - 10.5220/0003835203270333
PB - SciTePress