Authors:
Marco Gomes
1
;
Gabriel Falcão
1
;
Vitor Silva
1
;
Miguel Falcão
2
and
Pedro Faia
3
Affiliations:
1
Institute of Telecommunications, University of Coimbra; University of Coimbra, Portugal
;
2
Chipidea Microelectronica SA, Portugal
;
3
University of Coimbra, Portugal
Keyword(s):
LDPC, HDL, DVB-S2, Iterative Decoding, Scheduling, Tanner Graph.
Related
Ontology
Subjects/Areas/Topics:
Digital Audio and Video Broadcasting
;
Error Control and Concealment
;
Joint Source/Channel Coding
;
Multimedia
;
Multimedia and Communications
;
Telecommunications
Abstract:
This paper proposes an efficient HDL library of processing units for generic and DVB-S2 LDPC decoders following a modular and automatic design approach. General purpose, low complexity and high throughput bit node and check node functional models are developed. Both full serial and parallel architecture versions are considered. Also, a dedicated functional unit for an array processor LDPC decoder architecture to the DVB-S2 standard is considered. Additionally, it is described an automatic HDL code generator tool for arbitrary decoder architectures and LDPC codes, based on the proposed processing units and Matlab scripts.