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3 A MOTOR CONTROL SYSTEM
WITH ACM
Here we use an example application system case
study to demonstrate the usefulness of these kinds of
ACM models.
Figure 12 shows the basic structure of a
distributed motor control system found in (Kappos et
al 1990). The vC and iC blocks are the velocity and
current/torque controllers, both integrated into the
same ASIC in (Kappos et al 1990). The velocity and
current control laws are implemented digitally.
Because of the different speed requirements (the
inner loop requiring considerably faster control
actions than the outer one), the digital parts of the
ASIC controller were implemented in a dual-speed
fashion. The link between vC and iC is in effect
implemented as an analogue connection, with the
digital output from vC first converted into analogue
then re-sampled to provide the input for iC.
This kind of temporal decoupling is essential in
these kinds of distributed systems. In motor control
systems especially, if the inner and outer loops are
not temporally decoupled, potential digital hazards
such as deadlocks can propagate through from one
loop to another. The function of the inner control
loop is normally safety-critical, because even
temporary failure there could have catastrophic
effects such as causing the power electronic
elements or fuses to fail. If such a motor is used in a
safety-critical application (for instance in an
aeroplane fuel pump), such failures which cannot be
recovered on-line must always be avoided. As a
result, the capability of the inner loop to continue
functioning even when the outer loop has stopped
working is of vital importance. This means that even
though both vC and iC may be integrated into the
same piece of silicon, they must in reality be
temporally independent of each other.
Because of the difference in speed requirements
for the vC and iC parts, assuming the same
technology is being used to implement them in
hardware, the part of the hardware where vC is
implemented could have large amounts of excess
computational capacity. This makes it attractive to
attempt to make use of this capacity for other tasks,
i.e. to effectively implement the vC part as one of
the threads in a multi-tasking processing element.
This makes it possible for its progress to be affected
by other factors outside the immediate control
system boundary. Well-implemented operating
systems such as real-time kernels may take care of
the safety-critical implications of such complications
by ensuring that critical threads do not wait for
information from other threads.
At the basic hardware level of the data
connection between the iC and vC parts of an
embedded hard-wired controller chip, this kind of
non-blocking communication can be implemented
by using an analogue link. However, this implies an
analogue/digital hybrid chip.
- -
M iC vC
θ
d
θ
i
With ACMs, the same kind of temporal
decoupling can be realized without resorting to
inserting an analogue wire between two digital
devices. The OW-RR-BB type ACMs, especially,
mimics this function of an analogue wire perfectly.
When an OW-RR-BB is “full”, the writer overwrites
one of the items in it instead of waiting for a space
to appear, and when it is “empty” the reader rereads
the item it read during the previous cycle instead of
waiting for a new item to appear. This is
functionally the same as connecting the writer with
the reader through a D/A and A/D converter pair,
assuming perfect level-matching in the converters.
Figure 12 Schematic of dual-loop motor control system
We have implemented a Stateflow OW-RR-BB
ACM model using the techniques outlined in the
previous section. It was then inserted into a
MATLAB model of the system in Figure 12.
Figure 13 shows the way in which an OW-RR-
BB ACM was used to connect the fast and slow
controllers in the motor control system. The iC part
of the control law has a sampling frequency of 30
kHz and the vC part of the control law has a
sampling frequency of 1 kHz. Our simulations with
a single-cell OW-RR-BB ACM show that the reader
part of the ACM reads each data item approximately
30 times, as expected, and overwriting rarely
occurred. Some artificial perturbations were put into
the frequencies of the clock signals going into both
the vC and iC parts as a form of noise.
iC – fast ACM
i feedback
vC – slow
Figure 13: ACM connecting fast and slow circuits
The simulation results were compared with
results from simulating an entirely analogue version
of the same system. There were no detectable
differences from the output waveforms of both θ and
i. This is expected because an OW-RR-BB ACM is
ICINCO 2004 - SIGNAL PROCESSING, SYSTEMS MODELING AND CONTROL
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