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The design process of FPGA based systems includes the main stages referred
next. In the USB2-FPGA development system most of the design stages use the
Quartus II Web Edition design tools from Altera.
• Description
The system behavior and/or structure is defined from the design specifica-
tions. Schematics are used to describe the system structure and hardware de-
scription languages, like VHDL or Verilog, are used for the behavioral descrip-
tion. Usually a joint description combining both structural and behavioral ones is
used to define a specific system.
• Compilation
During compilation a netlist containing all the system components and their
interconnections is obtained, the right connection of the components is verified
and possible syntax errors are detected. Optionally, the netlist can be optimized
in order to improve the logic and interconnection resources usage.
The resultant netlist is used for the implementation and verification stages.
• Implementation
In this stage FPGA logic resources are assigned to the different elements of
the netlist (mapping process), placed and interconnected (place & route process
or fitting process). Besides, the FPGA programming file is generated and a new
netlist containing the delay of all signals is obtained.
Using the updated netlist a timing simulation or a timing analysis can be ac-
complish in order to verify the right operation of the designed system. If verifi-
cation results are the expected ones the FPGA can be programmed and the de-
sign is finished.
• Verification
Verification stage can be divided into three different processes: functional
simulation, timing simulation and timing analysis. By means of functional simu-
lation the system behavior can be verified without any timing consideration.
When good results are reached the system can be implemented and if not the
description must be modified.
Timing simulation and analysis take place after the implementation. Accord-
ing to the results of these processes the following actions must be accomplished
by the designer:
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When the system does not match the design specifications the descrip-
tion must be modified in order to correct possible errors.
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If the system does not work properly due, for example, to excessive
signal delays, one of these solutions must be executed:
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Back to the compilation or implementation stages to change options.
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Back to the description stage if the results are not the expected once
the compilation and implementation options have been modified.
• Programming
The FPGA is programmed using the USB2-FPGA Control Panel tool.
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