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HDL LIBRARY OF PROCESSING UNITS FOR GENERIC AND
DVB-S2 LDPC DECODING
Marco Gomes
1,2
, Gabriel Falcão
1,2
, João Gonçalves
1,2
, Vitor Silva
1,2
, Miguel Falcão
3
, Pedro Faia
2
1
Institute of Telecommunications, University of Coimbra, Coimbra, Portugal
2
Department of Electrical and Computer Engineering, University of Coimbra, Coimbra, Portugal
3
Chipidea Microelectronica SA, Porto, Portugal
Keywords: LDPC, HDL, DVB-S2, Iterative Decoding, Scheduling, Tanner Graph.
Abstract: This paper proposes an efficient HDL library of processing units for generic and DVB-S2 LDPC decoders
following a modular and automatic design approach. General purpose, low complexity and high throughput
bit node and check node functional models are developed. Both full serial and parallel architecture versions
are considered. Also, a dedicated functional unit for an array processor LDPC decoder architecture to the
DVB-S2 standard is considered. Additionally, it is described an automatic HDL code generator tool for
arbitrary decoder architectures and LDPC codes, based on the proposed processing units and Matlab scripts.
1 INTRODUCTION
Low Density Parity-Check (LDPC) codes (Gallager
1962; MacKay & Neal 1996) are among the most pow-
erful forward error correction codes known and can be
applied in a vast number of applications, from data
storage to telecommunications. The existence of effi-
cient coding and decoding algorithms combined with
their good decoding performance called the attention of
the scientific community and led already to their inclu-
sion in the recent digital video satellite broadcasting
standard (DVB-S2) (ETSI 2005). Although simple, the
decoding algorithm presents a significant challenge
from the hardware implementation point of view.
LDPC codes are a sub-set of linear block codes,
defined by sparse parity check matrix H, to which a
Tanner graph (Tanner 1981) can be coupled as for any
linear block code. This bipartite graph is formed by two
types of nodes, Check Nodes (CN), one per each code
constraint (H rows), and Bit Nodes (BN), one per each
bit of the codeword (H columns), with the connections
between them given by H.
The importance of the Tanner graph is reinforced
by the fact that best known LDPC decoding algorithms,
namely the Sum Product Algorithm (SPA) (Gallager
1962; Chen & Fossorier 2002), are all derived from the
Tanner Graph structure. The iterative procedure is
based on an exchange of messages between the BN’s
and CN’s of the Tanner graph, containing believes
about the value of each codeword bit with these mes-
sages (probabilities) being represented rigorously in
their domain or, more compactly, using logarithm like-
lihood ratios (LLR). The iterative procedure stops
when a valid codeword is achieved or the maximum
number of iterations is attained (in this case a decoder
failure is declared). A simple iterative decoder can thus
be constructed by considering each CN and BN of the
Tanner graph as processing units, and the connections
between them as bidirectional communication channels
through which the processed information is sent. In this
paper we propose a generic hardware implementation
for the CN and BN processing units.
A full parallel decoder is impracticable when con-
sidering codes of length 64800, as the ones that are
proposed for the DVB-S2 standard, because of the
large silicon area that would be needed for an imple-
mentation of this type, imposed not only by the high
number of processing units, but also by the huge num-
ber of connections between them (which imposes
severe routing problems).
Following this line of thought Kienle et al. (2005)
have proposed a partial parallel architecture with proc-
essing units being shared by groups of nodes, which
allows a drastic reduction of the used silicon area.
Another advantage of their proposed implementation is
the fact that it explores the particular characteristics,
namely, the periodicities, of the sub-set of LDPC codes
adopted by the DVB-S2 standard (ETSI 2005), known
as LDPC-IRA (LDPC - Irregular Repeat and
Accumulate Codes). This allows the decoder to work in
a reconfigurable way.
17
Gomes M., Falcão G., Silva V., Falcão M. and Faia P. (2006).
HDL LIBRARY OF PROCESSING UNITS FOR GENERIC AND DVB-S2 LDPC DECODING.
In Proceedings of the International Conference on Signal Processing and Multimedia Applications, pages 17-24
DOI: 10.5220/0001570000170024
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