Simulator for Real-Time Abstract State Machines

P. Vasilyev

2006

Abstract

We describe a concept and design of a simulator of Real-Time Abstract State Machines. Time can be continuous or discrete. Time constraints are defined by linear inequalities. Two semantics are considered: with and without non-deterministic bounded delays between actions. Simulation tasks can be generated according to descriptions in a special language. The simulator will be used for on-the-fly verification of formulas in an expressible timed predicate logic. Several features facilitating the simulation are described: external functions definition, delays settings, constraints specification, and others.

References

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Paper Citation


in Harvard Style

Vasilyev P. (2006). Simulator for Real-Time Abstract State Machines . In Proceedings of the 4th International Workshop on Modelling, Simulation, Verification and Validation of Enterprise Information Systems - Volume 1: MSVVEIS, (ICEIS 2006) ISBN 978-972-8865-49-8, pages 202-205. DOI: 10.5220/0002501002020205


in Bibtex Style

@conference{msvveis06,
author={P. Vasilyev},
title={Simulator for Real-Time Abstract State Machines},
booktitle={Proceedings of the 4th International Workshop on Modelling, Simulation, Verification and Validation of Enterprise Information Systems - Volume 1: MSVVEIS, (ICEIS 2006)},
year={2006},
pages={202-205},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0002501002020205},
isbn={978-972-8865-49-8},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 4th International Workshop on Modelling, Simulation, Verification and Validation of Enterprise Information Systems - Volume 1: MSVVEIS, (ICEIS 2006)
TI - Simulator for Real-Time Abstract State Machines
SN - 978-972-8865-49-8
AU - Vasilyev P.
PY - 2006
SP - 202
EP - 205
DO - 10.5220/0002501002020205