or detailed, the data exchangebetween differentnodes
via the channels is frame based or on bit level. To al-
low an easy exchange of the two models, abstract and
detailed model provide the same interface to the host.
This so called controller host interface (CHI) is part
of the CC. In the FlexRay specification the interface
functions are only roughly described, therefore this
basic description has to be filled to realize a precise
model.
In the following the models are described in more
detail. First there will be a short description of the
CHI, which is an important part of the abstract and the
detailed model, because it provides the same interface
towards an upper layer. Afterwards the abstract and
the detailed CC models will be explained.
5.2 Model Elements
5.2.1 Controller Host Interface
The CHI is responsible for the data and control flow
between CC and host. Beside the function as inter-
face, the CHI administrates the transmission and re-
ception buffer, manages the reception filter and pro-
vides access to configuration and status data. Both
reception and transmission buffer are CHI local mem-
ories, the same applies for the reception filter. The re-
ceive and transmission buffers are implemented with
unrestricted capacity. With regards to the primary
aims of the library it is not necessary to take limited
buffers into account. Each buffer is realized as a vec-
tor of data elements containing the relevant informa-
tion, example given frame identifier, channel, payload
length and payload data.
The CHI has two different interfaces, one to the
host by using the mentioned service based data struc-
ture and a second interface towards the CC protocol
functions. This second data structure can be inter-
preted as purely signal based. It is derived from the
protocol’s internal communication and contains a sig-
nal identifier and a field for additional data. A host
has write access to the transmission buffer and read
access to the reception buffer by using CHI services.
On the other side the protocol can use signals to write
received data into the reception buffer and to retrieve
data to send from the transmission buffer.
Each CC contains its own configuration, these
communication parameters are realized as memories,
too. Write access to the memories is only possible by
using the CHI and the provided services. Each host
is responsible for the correct configuration of its own
CC. So for configuration aspects it is not necessary
to parameterize the CHI module. To support the cre-
ation of a host an additional library is provided allow-
ing initialization, configuration, message sending and
reception.
5.2.2 Abstract CC Model
The design of a model starts with the question: What
is the operational aim of the model? Creating a de-
tailed model the answer is easy, the model has to be
built as accurately as possible. To achieve this the
specification is used as blueprint. As mentioned be-
fore the abstract model should allow a system anal-
ysis or development of systems on a higher level,
e.g. to support decisions in an early stage of de-
velopment. The abstract model of the FlexRay CC
uses some simplifications concerning the clock syn-
chronization mechanism, the temporal behavior and
the frame based data transmission. An external cen-
tral time master called Global Clock (GC) is responsi-
ble for synchronization and the timing of the FlexRay
communication.
The GC generates the cluster wide valid time,
which is represented by the so called macroticks
(MT). Important protocol values like the slot counter
for both FlexRay channels and the cycle counter are
derived from the MT. Each controller needs infor-
mation about important time events. In a FlexRay
cluster these are the slot starts. The GC announce a
change of the slot counter to all controllers. A con-
troller retrieves the actual counter values and checks,
if valid transmission data is available. In addition to
the medium access control the protocol model is also
responsible for data transmission and reception.
The description of the model can be divided into
two parts, one is the interface and the other is the
functionality and structure. Basic information about
the interfaces are already given, on one side of the
controller it is the well known CHI and on the other
side the controller communicates with the channel via
a data structure. This channel data structure contains
all relevantdata: frame identifier, payload data length,
cycle count, payload data and also some data for ad-
ministrative tasks, e.g. an error indicator. The ab-
stract model consists of the following modules: CHI,
UpdateStatus, SendtoChannel and ProcessRecData.
As shown in Figure 3 the controller has two mod-
ules SendtoChannel and two modules ProcessRec-
Data, one connected to channel A and one connected
to channel B. Each module itself has a complex in-
ternal structure consisting of further blocks based on
modules, MLDesigner primitives and newly devel-
oped custom primitives. The internal structure of the
modules will not be discussed in detail.
The module UpdateStatus receives events gener-
ated by the GC, updates the local time and triggers the
module SendtoChannel when a new slot starts. This
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