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5 CONCLUSIONS
This paper presented the evaluation results of sev-
eral FPGA implementations of K2 v2.0: high
speed implementations and compact implementa-
tions. The quad-keystream implementation is ex-
pected to achieved 5 Gbps on a Spartan-3 FPGA im-
plementation, and the circuit size of the compact im-
plementation of K2 is 2133 on Spartan-II. Further-
more, we evaluated the efficiency of the implementa-
tions using two benchmarks: throughput per area and
the normalized efficiency. The implementationsof K2
has high efficiency compared with other stream ci-
phers, and its efficiency is 4-10 times higher than AES
implementations. The evaluation results suggested
that the FPGA implementation of K2 is suitable for
applications using high speed encryption/decryption.
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