![](bg6.png)
limits the possible SNR. The noise is kept at a level
of 1 mV, which limits the filter accuracy by c. 6 dB
(1 bit). The accuracy is lower in case of high-pass
filters, which is due to additional signal inverting.
On the other hand the data rate significantly
differs between simulations and measurements. The
lower data rate attained in measurements is due to
large capacitances of pads as well as the setup
environment. The conclusion is that when the filter
is part of a bigger system, in which the output analog
signals are further processed in the chip, the data
rate can be higher and closer to the simulation
results. In this case energy dissipated per calculation
of a single pixel will be much smaller.
4 CONCLUSIONS
A 2-D analog, current-mode FIR filter has been
proposed in this paper. The main building block in
our filter is the Gilbert scalar-by-vector multiplier
that allows for an ultra-low power dissipation due to
transistors operating in weak inversion.
The proposed filter is a programmable solution,
with a very simple logic block and small number of
programming bits that allow for realization of
different filter masks both the high-pass and the low-
pass. One of the main advantages is a parallel and
asynchronous calculation of all output pixels without
using clock generators that typically are source of
feedthrough noise.
To verify the proposed idea, three experimental
image filters with different transistor dimensions
have been designed in a 180 nm CMOS technology.
Attenuation observed in post-layout HSPICE
simulations reaches a level of about 55 dB.
Theoretical analysis and measurement results
concerning the influence of the transistor-threshold-
voltage mismatch on the filter properties shows that
even in the worst case scenario, attenuation higher
than 36-dB (6 bits) can be achieved, for the
mismatch that is at the level of 2-3 %, which is
sufficient for many practical applications e.g. in
endoscopic capsules. The attained lower attenuation
is caused by an environmental noise that is present
in the input signal, as shown in Fig. 8 (top).
The filter performance is summarized in Table 3.
The data rate is given in image frames/s as in our
proposed filter this parameter does not depend on
number of pixels in a single frame. The data rate
attained in measurement significantly exceeds those
usually required is endoscopic capsules i.e. several
frames/s (Xie et al., 2006). This creates the
possibility to switch off the circuit for most of the
time and to save energy, which is one of the key
criteria in wireless endoscopic capsules.
Table 3: Summary of the image filters performance.
Parameter Small signals Large signals
Voltage supply 0.8 V 0.8 V
effective data rate(measur.) 15 kframes/s 15 kframes/s
effective data rate(simulate.) 350 kframes/s 1 Mframes/s
SNR (dB) 21-24 (3-4 bits) 30-36 (5-6 bits)
Power dissipation (6 pixels) 5 μW 30 μW
Energy/pixel (measured) 55 pJ 250 pJ
Energy/pixel (simulated) 2.3 pJ 5 pJ
Process TSMC CMOS 0.18 μm
Die area - one filter: 6 pixels 350 x 150 μm (0.052 mm
2
)
Image/mask resolution 6 x 1 / 3 x 1
ACKNOWLEDGEMENTS
The work is supported by EU Marie Curie Outgoing
International Fellowship No.
021926
REFERENCES
Meng, M.Q.-H. Tao Mei, Jiexin Pu, Chao Hu, Xiaona
Wang, Yawen Chan, “Wireless robotic capsule
endoscopy: state-of-the-art and challenges”, 5th World
Congress on Intelligent Control and Automation
(WCICA), 2004, Vol. 6, June 2004, pp.5561 - 5555
X. Xie, G. Li, X. Chen, X. Li, Z. Wang, “A Low-Power
Digital IC Design Inside the Wireless Endoscopic
Capsule”, IEEE Journal of Solid-State Circuits, Vol.
41, Issue 11, Nov. 2006, pp. 2390 - 2400
Shaou-Gang Miaou, Shih-Tse Chen, Fu-Sheng Ke,
“Capsule endoscopy image coding using wavelet-
based adaptive vector quantization without codebook
training”, 3rd International Conference on Information
Technology and Applications (ICITA), Vol. 1, July
2005, pp. 634 - 637
C. Winstead, Analog Iterative Error Control Decoders,
Ph.D disserta-tion, University of Alberta, ECE
Department, Edmonton, ABa, 2004.
G. Linan, P. Foldesy, S. Espejo, R. Dominguez-Castro, A.
Rodriguez-Vazquez, “A 0.5µm CMOS 106 transistors
analog programmable array processor for real–time
image processing”, 25th European Solid-State Circuits
Conference (ESSCIRC), 1999, pp. 358-361.
R. Serrano-Gotarredona, T. Serrano-Gotarredona, A.
Acosta-Jimenez, C. Serrano-Gotarredona, J. A. Perez-
Carrasco, A. Linares-Barranco, G. Jimenez-Moreno,
A. Civit-Ballcels, and B. Linares-Barranco, "On Real-
Time AER 2D Convolutions Hardware for
Neuromorphic Spike Based Cortical Processing,"
IEEE Trans. on Neural Networks, vol.19, No.7, pp.
1196-1219, July 2008
AN ASYNCHRONOUS PROGRAMMABLE PARALLEL 2-D IMAGE FILTER CMOS IC BASED ON THE GILBERT
VECTOR MULTIPLIER
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