![](bg6.png)
Table 3: Global resource utilization.
Fully parallel Folded
Resource Qty. % Qty. %
Slices 5,115 37% 6,680 86%
Flip Flops 4,010 14% 4,743 30%
Input LUTs 6,686 24% 11,009 71%
IOBs 44 7% 43 24%
Block RAM 1 24% 1 68%
Block ROM 8 2% 5 13%
Multipliers 91 67% 13 54%
Because they are based on the same architecture, both
arrays produce the same results. Figure 6 shows the
waveforms obtained from the hardware implementa-
tion of the algorithm. The chips successfully produce
the ECG signal of the fetus, two ECG signals of the
mother, and the noise. Figure 7 compares the software
and hardware results for one waveform. We measured
the error of the results produced by the array relative
to the floating-point software implementation. The
RMS value of the error, normalized to the amplitude
of the signal, varies between 0.07% and 0.09%.
(a) Time(Sec)
Amplitude
0 0.2 0.4 0.6 0.8 1
−1
0
1
(b) Time(Sec)
Amplitude
0 0.2 0.4 0.6 0.8 1
−1
0
1
(c) Time(Sec)
Amplitude
0 0.2 0.4 0.6 0.8 1
−1
0
1
(d) Time(Sec)
Amplitude
0 0.2 0.4 0.6 0.8 1
−0.1
0
0.1
(e) Time(Sec)
Amplitude
0 0.2 0.4 0.6 0.8 1
−0.05
0
0.05
(f) Time(Sec)
Amplitude
0 0.2 0.4 0.6 0.8 1
−1
0
1
(g) Time(Sec)
Amplitude
0 0.2 0.4 0.6 0.8 1
−2
0
2
(h) Time(Sec)
Amplitude
Figure 6: (a)-(d): Measured mixtures, (e): ECG - fetus, (f):
Noise, (g)-(h): ECG - mother.
0 0.1 0.2 0.3 0.4 0.5
−3
−2
−1
0
1
2
3
Time(sec)
Normalized Amplitude
Software
Hardware
Figure 7: ECG results - fetus.
5 CONCLUSIONS
We described an array architecture for ICA using the
InfoMax algorithm. The array can be reconfigured
to target a wide range of FPGA devices, represent-
ing different price/performance tradeoffs. We showed
two configurations: a fully-parallel version mapped to
a Xilinx Virtex-II Pro XC2VP30, and a folded imple-
mentation mapped to a Xilinx Spartan-3 XC3S1000.
The parallel array outperforms both the folded config-
uration by a factor of 14.5, and a PC-based software
implementation by a factor of 11.3. Both hardware
arrays consume in the order of 100mW, use 18-bit
fixed-point arithmetic, and achieve a resolution within
0.08% of a floating-point software implementation of
the algorithm. Future and ongoing work includes de-
veloping a software tool to automate the reconfigura-
tion process, and integrating the folded version of the
array on a portable ECG instrument.
ACKNOWLEDGEMENTS
This work was partially funded by grants Fondecyt
1070485 and Milenio ICMP06-67F.
REFERENCES
Anguita, D., Boni, A., and Ridella, S. (2003). A digital ar-
chitecture for support vector machines: Theory, algo-
rithm, and FPGA implementation. IEEE Transactions
on Neural Networks, 14:993–1009.
Bell, A. J. and Sejnowski, T. J. (1997). The ’Independent
Components’ of Natural Scenes are Edge Filters. Vi-
sion Research, 37(23):3327–3338.
Cardoso, J. F. (1997). Infomax and maximum likelihood
for blind source separation. IEEE Signal Processing,
4:112–114.
Li, Z. and Lin, Q. (2005). FPGA implementation of In-
fomax BSS algorithm with fixed-point number repre-
sentation. Neural Networks and Brain, 2:889–892.
Potter, M., Gadhok, N., and Kinsner, W. (2002). Separation
performance of ICA on simulated EEG and ECG sig-
nals contaminated by noise. IEEE Canadian Confer-
ence on Electrical & Computer Engineering, 2:1099–
1104.
Yang, Y., Huang, X., and Yu, X. (2007). Real-time ECG
monitoring system based on FPGA. 33rd Annual Con-
ference of IEE Industrial Electronics Society, pages
2136–2140.
Zeng, Y., Liu, S., and Zhang, J. (2008). Extraction of fetal
ECG signal via adaptive noise cancellation approach.
The 2nd International Conference on Bioinformatics
and Biomedical Engineering, pages 2270–2273.
A RECONFIGURABLE ARRAY FOR BLIND SOURCE-SEPARATION ON AN FPGA
267