2002). Therefore, computer independence, portabil-
ity and low power consumption are required criteria.
BCIs based on SSVEP are not considered true BCIs
because the users have to gaze the specific stimulus
and therefore have to move the eyes. Notwithstanding
this, the interface can be suitable for people with se-
vere motor disabilities and unable to control standard
interfaces such as joysticks, head switches, voice or
eye trackers, but still able to perform small eye move-
ments.
The remaining sections of the paper describe the
design and implementation of the system still under
development, and also some preliminary results al-
ready reached.
2 MODULE ARCHITECTURE
The diagram on Figure 1 illustrates the proposed ar-
chitecture. The first module is a 6 channel EEG
amplifier that receives EEG signal picked from non-
invasive electrodes. The output signal is in the range
of 0 − 5V. The data acquisition module is a PIC
18F4550 (Microchip, 2008), which was configured to
sample the signal at a 512 Hz rate and was imple-
mented based on a real-time interrupt. The A/D con-
verter has a 10 bit resolution. The digital signal is
then sent via USB to a PC for data recording, mon-
itoring or real-time signal processing. If working on
stand-alone mode, digital data is sent via SPI to the
dsPIC 30F3013. The dsPIC is able to perform some
statistical computation, digital filtering and FFT com-
putation to extract signal features for classification.
The output from decoded patterns can be directly sent
to a control unit on the wheelchair. The last module is
a stimuli generator implemented on the PIC 18F458.
It controls a set of LEDs that can be activated sequen-
tially, randomly, or at a given frequency (Figure 5).
The module is therefore suitable to generate stimuli
for SSVEP and for P300. In the case of P300 opera-
tion, each stimulus code is sent to the dsPIC via SPI or
to the PC via USB or RS232. Table 1 presents some
of the main specifications of the system.
On the present development stage, only one am-
plifier channel was implemented. The signal process-
ing algorithms are not running at the dsPIC, but only
at the PC after signal recording.
2.1 Amplifier
EEG signals are characterized by having very low am-
plitude values, typically in the range of 5-100 µV, re-
quiring a very accurate conditioning in order to am-
plify input signals and reject the existing noise or in-
Figure 1: System architecture.
Table 1: Overall system specifications.
Number of channels 6
Resolution 10 bit
Min input voltage step detect 195nV
Input voltage full scale 200 µV
Input frequency range 0.25-45 Hz
CMRR 100-120 dB
Noise spectral density 339 nV/
p
(Hz)
Min and Max Gain 66-91 dB
Current per channel 6 mA
terferences. A high input impedance of the condition-
ing module avoid signal distortion due to loading ef-
fects.
An EEG amplifier module was developed for
signal conditioning and amplification. The mod-
ule design follows the OpenEEG project approach
(OpenEEG-Project, 2008). The main difference was
the insertion of a notch filter to reject the 50 Hz from
power line interference. This improvement made pos-
sible the use of standard electrodes, whilst the Ope-
nEEG project needs non-standard shielded electrodes.
The amplifier module is shown in Figure 2.
The EEG signals acquired from the electrodes pass
through the protection circuit who acts as a voltage
and current limiter. The instrumentation amplifier
with 28dB of gain is implemented with the INA128P
circuit that is characterized by having low offset volt-
age, typically 50 µV, and high Common Mode Re-
jection Ratio (CMRR) (between 100-120 dB). One
second-order high-pass filter with cut-off frequency
at 0.16 Hz and gain 15 to 40dB follows the INA128P
in order to increase the input signal amplitude and
to reject the DC component imposed by the ampli-
fier offset voltage. Then, the signal passes through
an anti-aliasing filter that is a third-order Bessel low-
pass filter with cut-off frequency of 45Hz and gain
22.4dB. In order to reject the 50Hz component, the
A LOW-COST EEG STAND-ALONE DEVICE FOR BRAIN COMPUTER INTERFACE
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