AN IMPROVED ON-CHIP DEBUG ARCHITECTURE FOR SPARC PROCESSOR BASED ON SHADOW SCAN TECHNIQUE

Liu Peng, Yu Lixin, Hui Qin

2011

Abstract

Because of the increasing design complexity of embedded microprocessors, pre–silicon verification in design stage is insufficient to eliminate bugs (electrical and functional) and nonconforming chip behaviour can still be found after the design is manufactured. Therefore, on–chip debug is becoming a key step both in the implementation flow for the purpose of identifying and fixing design errors that have escaped pre–silicon verification and in software development. In this paper, we present a new method of using improved shadow scan architecture in the debug procedure which involves general–purpose registers in OpenSPARC T2 processor and illustrate the mechanism of this logic and function module. The proposed architecture is suitable for debugging work in practical embedded application, and provides more observability and controllability which can reduce the time of scanning specified register window to 1/16 at the most.

References

  1. Chen Bilong, Yan Xiaolang, 2003. Method of Using Shadow Registers in designing an on-chip Debug Unit of a Microprocessor, Proc. Of International Conference on ASIC.
  2. Joon Sung Yang, 2009. Enhancing Silicon Debug Techniques via DFD Hardware Insertion, phD thesis.
  3. Xinli Gu, Weili Wang, Kevin Li, etc, 2002. Re-Using DFT Logic for Functional and Silicon Debugging Test, Proc. of International Test Conference.
  4. Farideh Golshan, 2003. Test and On-line Debug Capabilities of IEEE Std 1149.1 in UltraSPARC-III Microprocessor, Proc. of International Test Conference.
  5. Sun Microsystems, 2007. OpenSPARCT2 Programmer's Reference Manual.
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Paper Citation


in Harvard Style

Peng L., Lixin Y. and Qin H. (2011). AN IMPROVED ON-CHIP DEBUG ARCHITECTURE FOR SPARC PROCESSOR BASED ON SHADOW SCAN TECHNIQUE . In Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS, ISBN 978-989-8425-48-5, pages 441-444. DOI: 10.5220/0003361504410444


in Bibtex Style

@conference{peccs11,
author={Liu Peng and Yu Lixin and Hui Qin},
title={AN IMPROVED ON-CHIP DEBUG ARCHITECTURE FOR SPARC PROCESSOR BASED ON SHADOW SCAN TECHNIQUE},
booktitle={Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,},
year={2011},
pages={441-444},
publisher={SciTePress},
organization={INSTICC},
doi={10.5220/0003361504410444},
isbn={978-989-8425-48-5},
}


in EndNote Style

TY - CONF
JO - Proceedings of the 1st International Conference on Pervasive and Embedded Computing and Communication Systems - Volume 1: PECCS,
TI - AN IMPROVED ON-CHIP DEBUG ARCHITECTURE FOR SPARC PROCESSOR BASED ON SHADOW SCAN TECHNIQUE
SN - 978-989-8425-48-5
AU - Peng L.
AU - Lixin Y.
AU - Qin H.
PY - 2011
SP - 441
EP - 444
DO - 10.5220/0003361504410444